Datasheet Texas Instruments SN74ACT8997DWR
| Manufacturer | Texas Instruments |
| Series | SN74ACT8997 |
| Part Number | SN74ACT8997DWR |
Scan Path Linkers With 4-Bit Identification Buses Scan-Controlled TAP Concatenators 28-SOIC 0 to 70
Datasheets
Scan Path Linkers With 4-Bit Identification Buses Scan-Controlled IEEE Std datasheet
PDF, 1.0 Mb, Revision: D, File published: Dec 1, 1996
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 28 |
| Package Type | DW |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | ACT8997 |
| Width (mm) | 7.5 |
| Length (mm) | 17.9 |
| Thickness (mm) | 2.35 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.65 |
| Mechanical Data | Download |
Eco Plan
| RoHS | Compliant |
Application Notes
- Programming CPLDs Via the 'LVT8986 LASPPDF, 819 Kb, File published: Nov 1, 2005
This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
Model Line
Series: SN74ACT8997 (2)
- SN74ACT8997DW SN74ACT8997DWR
Manufacturer's Classification
- Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic
