Datasheet Texas Instruments SN74ALS112A
Manufacturer | Texas Instruments |
Series | SN74ALS112A |

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset
Datasheets
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset datasheet
PDF, 988 Kb, Revision: A, File published: Dec 1, 1994
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Prices
Status
SN74ALS112AD | SN74ALS112ADR | SN74ALS112AN | SN74ALS112AN3 | SN74ALS112ANSR | |
---|---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Obsolete (Manufacturer has discontinued the production of the device) | Active (Recommended for new designs) |
Manufacture's Sample Availability | No | No | No | No | No |
Packaging
SN74ALS112AD | SN74ALS112ADR | SN74ALS112AN | SN74ALS112AN3 | SN74ALS112ANSR | |
---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 |
Pin | 16 | 16 | 16 | 16 | 16 |
Package Type | D | D | N | N | NS |
Industry STD Term | SOIC | SOIC | PDIP | PDIP | SOP |
JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDIP-T | R-PDIP-T | R-PDSO-G |
Package QTY | 40 | 2500 | 25 | 2000 | |
Carrier | TUBE | LARGE T&R | TUBE | LARGE T&R | |
Device Marking | ALS112A | ALS112A | SN74ALS112AN | ALS112A | |
Width (mm) | 3.91 | 3.91 | 6.35 | 6.35 | 5.3 |
Length (mm) | 9.9 | 9.9 | 19.3 | 19.3 | 10.3 |
Thickness (mm) | 1.58 | 1.58 | 3.9 | 3.9 | 1.95 |
Pitch (mm) | 1.27 | 1.27 | 2.54 | 2.54 | 1.27 |
Max Height (mm) | 1.75 | 1.75 | 5.08 | 5.08 | 2 |
Mechanical Data | Download | Download | Download | Download | Download |
Parametrics
Parameters / Models | SN74ALS112AD![]() | SN74ALS112ADR![]() | SN74ALS112AN![]() | SN74ALS112AN3![]() | SN74ALS112ANSR![]() |
---|---|---|---|---|---|
Approx. Price (US$) | 0.44 | 1ku | 0.44 | 1ku | |||
Bits | 2 | 2 | 2 | ||
Bits(#) | 2 | 2 | |||
F @ Nom Voltage(Max), Mhz | 75 | 75 | 75 | ||
F @ Nom Voltage(Max)(Mhz) | 75 | 75 | |||
ICC @ Nom Voltage(Max), mA | 4.5 | 4.5 | 4.5 | ||
ICC @ Nom Voltage(Max)(mA) | 4.5 | 4.5 | |||
Input Type | TTL | ||||
Output Drive (IOL/IOH)(Max), mA | -0.4/8 | -0.4/8 | -0.4/8 | ||
Output Drive (IOL/IOH)(Max)(mA) | -0.4/8 | -0.4/8 | |||
Output Type | TTL | ||||
Package Group | SOIC | SOIC | PDIP | PDIP | SO |
Package Size: mm2:W x L, PKG | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | See datasheet (PDIP) | 16SO: 80 mm2: 7.8 x 10.2(SO) | ||
Package Size: mm2:W x L (PKG) | See datasheet (PDIP) | See datasheet (PDIP) | |||
Rating | Catalog | Catalog | Catalog | Catalog | Catalog |
Schmitt Trigger | No | No | No | No | No |
Technology Family | ALS | ALS | ALS | ALS | ALS |
VCC(Max), V | 5.5 | 5.5 | 5.5 | ||
VCC(Max)(V) | 5.5 | 5.5 | |||
VCC(Min), V | 4.5 | 4.5 | 4.5 | ||
VCC(Min)(V) | 4.5 | 4.5 | |||
Voltage(Nom), V | 5 | 5 | 5 | ||
Voltage(Nom)(V) | 5 | 5 | |||
tpd @ Nom Voltage(Max), ns | 18 | 18 | 18 | ||
tpd @ Nom Voltage(Max)(ns) | 18 | 18 |
Eco Plan
SN74ALS112AD | SN74ALS112ADR | SN74ALS112AN | SN74ALS112AN3 | SN74ALS112ANSR | |
---|---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Not Compliant | Compliant |
Pb Free | Yes | No | Yes |
Application Notes
- Advanced Schottky (ALS and AS) Logic FamiliesPDF, 1.9 Mb, File published: Aug 1, 1995
This document introduces the advanced Schottky family of clamped TTL integrated circuits (ICs). Detailed electrical characteristics of the 'AS and 'ALS devices with table formats are provided. Guidelines for designing high-performance digital systems using the Advanced Schottky family are given along with a brief summary of the solutions to most design decisions needed to implement systems using t
Model Line
Series: SN74ALS112A (5)
Manufacturer's Classification
- Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop