Datasheet Texas Instruments SN74ALVTH16373DLR
| Manufacturer | Texas Instruments |
| Series | SN74ALVTH16373 |
| Part Number | SN74ALVTH16373DLR |
2.5-V/3.3-V 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85
Datasheets
2.5-V/3.3-V 16-Bit Transparent D-Type Latches With 3-State Outputs datasheet
PDF, 825 Kb, Revision: F, File published: Jan 8, 1999
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Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 48 |
| Package Type | DL |
| Industry STD Term | SSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | ALVTH16373 |
| Width (mm) | 7.49 |
| Length (mm) | 15.88 |
| Thickness (mm) | 2.59 |
| Pitch (mm) | .635 |
| Max Height (mm) | 2.79 |
| Mechanical Data | Download |
Parametrics
| 3-State Output | Yes |
| Bits | 16 |
| F @ Nom Voltage(Max) | 250 Mhz |
| ICC @ Nom Voltage(Max) | 5 mA |
| Operating Temperature Range | -40 to 85 C |
| Output Drive (IOL/IOH)(Max) | 64/-32 mA |
| Package Group | SSOP |
| Package Size: mm2:W x L | 48SSOP: 164 mm2: 10.35 x 15.88(SSOP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | ALVT |
| VCC(Max) | 3.6 V |
| VCC(Min) | 2.3 V |
| Voltage(Nom) | 2.5,3.3 V |
| tpd @ Nom Voltage(Max) | 3.8,3.3 ns |
Eco Plan
| RoHS | Compliant |
Application Notes
- Advanced Low-Voltage TechnologyPDF, 59 Kb, File published: Jul 27, 1999
ALVT, the advanced low-voltage logic family, offers high-performance BiCMOS devices that are functional at 3.3-V and 2.5-V V sub CC and have low propagation delay, low static-power consumption, and 64 mA current drive. Other features include 5-V tolerance; auto3-state; bus hold; partial power down, hot insertion, and live insertion; and excellent simultaneous-switching and output-skew performance. - Bus-Hold CircuitPDF, 418 Kb, File published: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of - 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)PDF, 895 Kb, Revision: B, File published: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa - Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)PDF, 154 Kb, Revision: A, File published: Sep 8, 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families - Power-Up 3-State (PU3S) Circuits in TI Standard Logic DevicesPDF, 209 Kb, File published: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
Model Line
Series: SN74ALVTH16373 (8)
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch
