Datasheet Texas Instruments SN74AUC2G79
| Manufacturer | Texas Instruments |
| Series | SN74AUC2G79 |
Dual Positive-Edge-Triggered D-Type Flip-Flop
Datasheets
SN74AUC2G79 datasheet
PDF, 940 Kb, Revision: C, File published: Jan 15, 2007
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Prices
Status
| SN74AUC2G79DCTR | SN74AUC2G79DCUR | SN74AUC2G79YZPR | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | Yes | Yes |
Packaging
| SN74AUC2G79DCTR | SN74AUC2G79DCUR | SN74AUC2G79YZPR | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 8 | 8 | 8 |
| Package Type | DCT | DCU | YZP |
| Industry STD Term | SSOP | VSSOP | DSBGA |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-XBGA-N |
| Package QTY | 3000 | 3000 | 3000 |
| Carrier | LARGE T&R | LARGE T&R | LARGE T&R |
| Device Marking | Z | U79Q | URN |
| Width (mm) | 2.8 | 2 | 2.25 |
| Length (mm) | 2.95 | 2.3 | 1.25 |
| Thickness (mm) | 1.29 | .85 | .31 |
| Pitch (mm) | .65 | .5 | .5 |
| Max Height (mm) | 1.3 | .9 | .5 |
| Mechanical Data | Download | Download | Download |
Parametrics
| Parameters / Models | SN74AUC2G79DCTR | SN74AUC2G79DCUR | SN74AUC2G79YZPR |
|---|---|---|---|
| 3-State Output | No | No | No |
| Bits | 2 | 2 | 2 |
| F @ Nom Voltage(Max), Mhz | 250 | 250 | 250 |
| Gate Type | FLIP-FLOP | FLIP-FLOP | FLIP-FLOP |
| ICC @ Nom Voltage(Max), mA | 0.01 | 0.01 | 0.01 |
| Logic | True | True | True |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Drive (IOL/IOH)(Max), mA | 9/-9 | 9/-9 | 9/-9 |
| Package Group | SM8 | VSSOP | DSBGA |
| Package Size: mm2:W x L, PKG | 8SM8: 12 mm2: 4 x 2.95(SM8) | 8VSSOP: 6 mm2: 3.1 x 2(VSSOP) | See datasheet (DSBGA) |
| Rating | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No |
| Special Features | IOFF,low power consumption,low tpd | IOFF,low power consumption,low tpd | IOFF,low power consumption,low tpd |
| Sub-Family | D-Type Flip-Flop | D-Type Flip-Flop | D-Type Flip-Flop |
| Technology Family | AUC | AUC | AUC |
| VCC(Max), V | 2.7 | 2.7 | 2.7 |
| VCC(Min), V | 0.8 | 0.8 | 0.8 |
| Voltage(Nom), V | 0.8,1.2,1.5,1.8,2.5 | 0.8,1.2,1.5,1.8,2.5 | 0.8,1.2,1.5,1.8,2.5 |
| tpd @ Nom Voltage(Max), ns | 5,3.9,2.5,1.9,1.3 | 5,3.9,2.5,1.9,1.3 | 5,3.9,2.5,1.9,1.3 |
Eco Plan
| SN74AUC2G79DCTR | SN74AUC2G79DCUR | SN74AUC2G79YZPR | |
|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant |
Application Notes
- Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus DevicesPDF, 374 Kb, File published: Mar 21, 2003
System designers are continuously seeking ways to improve signal integrity, increase speed, and reduce power consumption in personal computers, telecommunication equipment, and other electronic systems. The Texas Instruments (TI) next-generation Advanced Ultra-low-voltage CMOS (AUC) octals and Widebus(TM) devices are designed to achieve these goals. These devices are designed for a 0.8-V to 2.7-V
Model Line
Series: SN74AUC2G79 (3)
Manufacturer's Classification
- Semiconductors> Logic> Little Logic
