Datasheet Texas Instruments SN74AUC32

ManufacturerTexas Instruments
SeriesSN74AUC32
Datasheet Texas Instruments SN74AUC32

Quadruple 2-Input Positive-OR Gate

Datasheets

SN74AUC32 datasheet
PDF, 573 Kb, Revision: A, File published: Mar 29, 2005
Extract from the document

Prices

Status

SN74AUC32RGYRSN74AUC32RGYRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYes

Packaging

SN74AUC32RGYRSN74AUC32RGYRG4
N12
Pin1414
Package TypeRGYRGY
Industry STD TermVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-N
Package QTY30003000
CarrierLARGE T&RLARGE T&R
Device MarkingMS32MS32
Width (mm)3.53.5
Length (mm)3.53.5
Thickness (mm).9.9
Pitch (mm).5.5
Max Height (mm)11
Mechanical DataDownloadDownload

Parametrics

Parameters / ModelsSN74AUC32RGYR
SN74AUC32RGYR
SN74AUC32RGYRG4
SN74AUC32RGYRG4
Bits44
F @ Nom Voltage(Max), Mhz250250
ICC @ Nom Voltage(Max), mA0.010.01
Operating Temperature Range, C-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA9/-99/-9
Package GroupVQFNVQFN
Package Size: mm2:W x L, PKG14VQFN: 12 mm2: 3.5 x 3.5(VQFN)14VQFN: 12 mm2: 3.5 x 3.5(VQFN)
RatingCatalogCatalog
Schmitt TriggerNoNo
Technology FamilyAUCAUC
VCC(Max), V2.72.7
VCC(Min), V0.80.8
Voltage(Nom), V0.8,1.2,1.5,1.8,2.50.8,1.2,1.5,1.8,2.5
tpd @ Nom Voltage(Max), ns5.3,3.5,2.7,2.2,1.35.3,3.5,2.7,2.2,1.3

Eco Plan

SN74AUC32RGYRSN74AUC32RGYRG4
RoHSCompliantCompliant

Application Notes

  • Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices
    PDF, 374 Kb, File published: Mar 21, 2003
    System designers are continuously seeking ways to improve signal integrity, increase speed, and reduce power consumption in personal computers, telecommunication equipment, and other electronic systems. The Texas Instruments (TI) next-generation Advanced Ultra-low-voltage CMOS (AUC) octals and Widebus(TM) devices are designed to achieve these goals. These devices are designed for a 0.8-V to 2.7-V

Model Line

Series: SN74AUC32 (2)

Manufacturer's Classification

  • Semiconductors> Logic> Gate> OR Gate