Datasheet Texas Instruments SN74AVC16722

Manufacturer	Texas Instruments
Series	SN74AVC16722

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Parametrics

Parameters / Models	74AVC16722DGGRE4	SN74AVC16722DGGR
3-State Output	Yes	Yes
Bits	22	22
F @ Nom Voltage(Max), Mhz	200	200
ICC @ Nom Voltage(Max), mA	0.04	0.04
Operating Temperature Range, C	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	12/-12	12/-12
Package Group	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	64TSSOP: 138 mm2: 8.1 x 17(TSSOP)	64TSSOP: 138 mm2: 8.1 x 17(TSSOP)
Rating	Catalog	Catalog
Schmitt Trigger	No	No
Technology Family	AVC	AVC
VCC(Max), V	3.6	3.6
VCC(Min), V	1.2	1.2
Voltage(Nom), V	1.2,1.5,1.8,2.5,3.3	1.2,1.5,1.8,2.5,3.3
tpd @ Nom Voltage(Max), ns	7.7,6.3,5.4,3.3,2.6	7.7,6.3,5.4,3.3,2.6

Eco Plan

Application Notes

• Download
  Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)
  PDF, 126 Kb, Revision: B, File published: Jul 7, 1999
  Texas Instruments (TI[TM]) next-generation logic is called the Advanced Very-low-voltage CMOS (AVC) family. The AVCfamily features TI?s Dynamic Output Control (DOC[TM]) circuit (patent pending). DOC circuitry automatically lowers the outputimpedance of the circuit at the beginning of a signal transition, providing enough current to achieve high signaling speeds, thensubsequently raises the i
• Download
  AVC Logic Family Technology and Applications (Rev. A)
  PDF, 148 Kb, Revision: A, File published: Aug 26, 1998
  Texas Instruments (TI?) announces the industry?s first logic family to achieve maximum propagation delays of less than 2 ns at 2.5 V. TI?s next-generation logic is the Advanced Very-low-voltage CMOS (AVC) family. Although optimized for 2.5-V systems, AVC logic supports mixed-voltage systems because it is compatible with 3.3-V and 1.8-V devices. The AVC family features TI?s Dynamic Output Control (
• Download
  Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)
  PDF, 390 Kb, Revision: B, File published: Apr 30, 2015
• Download
  16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
  PDF, 895 Kb, Revision: B, File published: May 22, 2002
  TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
• Download
  Selecting the Right Level Translation Solution (Rev. A)
  PDF, 313 Kb, Revision: A, File published: Jun 22, 2004
  Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
• Download
  Power-Up Behavior of Clocked Devices (Rev. A)
  PDF, 34 Kb, Revision: A, File published: Feb 6, 2015

Model Line

Manufacturer's Classification

• Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop