Datasheet Texas Instruments SN74F112
| Manufacturer | Texas Instruments |
| Series | SN74F112 |
Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset
Datasheets
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset datasheet
PDF, 639 Kb, Revision: A, File published: Oct 1, 1993
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Prices
Status
| SN74F112D | SN74F112DR | SN74F112DRE4 | SN74F112DRG4 | SN74F112N | SN74F112NE4 | SN74F112NSR | SN74F112NSRE4 | SN74F112NSRG4 | |
|---|---|---|---|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No | Yes | No | No | No | No | No | No |
Packaging
| SN74F112D | SN74F112DR | SN74F112DRE4 | SN74F112DRG4 | SN74F112N | SN74F112NE4 | SN74F112NSR | SN74F112NSRE4 | SN74F112NSRG4 | |
|---|---|---|---|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
| Pin | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| Package Type | D | D | D | D | N | N | NS | NS | NS |
| Industry STD Term | SOIC | SOIC | SOIC | SOIC | PDIP | PDIP | SOP | SOP | SOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDIP-T | R-PDIP-T | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 40 | 2500 | 2500 | 2500 | 25 | 25 | 2000 | 2000 | 2000 |
| Carrier | TUBE | LARGE T&R | LARGE T&R | LARGE T&R | TUBE | TUBE | LARGE T&R | LARGE T&R | LARGE T&R |
| Device Marking | F112 | F112 | F112 | F112 | SN74F112N | SN74F112N | 74F112 | 74F112 | 74F112 |
| Width (mm) | 3.91 | 3.91 | 3.91 | 3.91 | 6.35 | 6.35 | 5.3 | 5.3 | 5.3 |
| Length (mm) | 9.9 | 9.9 | 9.9 | 9.9 | 19.3 | 19.3 | 10.3 | 10.3 | 10.3 |
| Thickness (mm) | 1.58 | 1.58 | 1.58 | 1.58 | 3.9 | 3.9 | 1.95 | 1.95 | 1.95 |
| Pitch (mm) | 1.27 | 1.27 | 1.27 | 1.27 | 2.54 | 2.54 | 1.27 | 1.27 | 1.27 |
| Max Height (mm) | 1.75 | 1.75 | 1.75 | 1.75 | 5.08 | 5.08 | 2 | 2 | 2 |
| Mechanical Data | Download | Download | Download | Download | Download | Download | Download | Download | Download |
Parametrics
| Parameters / Models | SN74F112D | SN74F112DR | SN74F112DRE4 | SN74F112DRG4 | SN74F112N | SN74F112NE4 | SN74F112NSR | SN74F112NSRE4 | SN74F112NSRG4 |
|---|---|---|---|---|---|---|---|---|---|
| Bits | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| F @ Nom Voltage(Max), Mhz | 70 | 70 | 70 | 70 | 70 | 70 | 70 | 70 | 70 |
| ICC @ Nom Voltage(Max), mA | 19 | 19 | 19 | 19 | 19 | 19 | 19 | 19 | 19 |
| Output Drive (IOL/IOH)(Max), mA | -1/20 | -1/20 | -1/20 | -1/20 | -1/20 | -1/20 | -1/20 | -1/20 | -1/20 |
| Package Group | SOIC | SOIC | SOIC | SOIC | PDIP | PDIP | SO | SO | SO |
| Package Size: mm2:W x L, PKG | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | See datasheet (PDIP) | See datasheet (PDIP) | 16SO: 80 mm2: 7.8 x 10.2(SO) | 16SO: 80 mm2: 7.8 x 10.2(SO) | 16SO: 80 mm2: 7.8 x 10.2(SO) |
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No | No | No | No | No | No | No |
| Technology Family | F | F | F | F | F | F | F | F | F |
| VCC(Max), V | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 |
| VCC(Min), V | 4.5 | 4.5 | 4.5 | 4.5 | 4.5 | 4.5 | 4.5 | 4.5 | 4.5 |
| Voltage(Nom), V | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 |
| tpd @ Nom Voltage(Max), ns | 7.5 | 7.5 | 7.5 | 7.5 | 7.5 | 7.5 | 7.5 | 7.5 | 7.5 |
Eco Plan
| SN74F112D | SN74F112DR | SN74F112DRE4 | SN74F112DRG4 | SN74F112N | SN74F112NE4 | SN74F112NSR | SN74F112NSRE4 | SN74F112NSRG4 | |
|---|---|---|---|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
| Pb Free | Yes | Yes |
Model Line
Series: SN74F112 (9)
Manufacturer's Classification
- Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop
