Datasheet Texas Instruments SN74GTLP1395PWR

Manufacturer	Texas Instruments
Series	SN74GTLP1395
Part Number	SN74GTLP1395PWR

Two 1-Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-TSSOP -40 to 85

Datasheets

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PDF, 1.2 Mb, Revision: C, File published: Jan 3, 2006

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Prices

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

Packaging

Pin	20
Package Type	PW
Industry STD Term	TSSOP
JEDEC Code	R-PDSO-G
Package QTY	2000
Carrier	LARGE T&R
Device Marking	GP395
Width (mm)	4.4
Length (mm)	6.5
Thickness (mm)	1
Pitch (mm)	.65
Max Height (mm)	1.2
Mechanical Data	Download

Parametrics

Bits	2
F @ Nom Voltage(Max)	175 Mhz
ICC @ Nom Voltage(Max)	20 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	100 mA
Package Group	TSSOP
Package Size: mm2:W x L	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	GTLP
VCC(Max)	3.45 V
VCC(Min)	3.15 V
Voltage(Nom)	3.3 V
tpd @ Nom Voltage(Max)	9.7 ns

Eco Plan

RoHS

Compliant

Application Notes

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Texas Instruments GTLP Frequently Asked Questions
PDF, 496 Kb, File published: Jan 1, 2001
Using a question-and-answer format, advantages of TI?s GTLP devices, particularly for backplane applications, are presented, as well as differences between GTLP and GTL/LVDS devices. Applicable topics include data throughput rates, synchronous clocks, price and alternative sources, bus transceivers, live insertion, power consumption, backplane termination, voltage translation, IBIS and HSPICE mode
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Logic in Live-Insertion Applications With a Focus on GTLP
PDF, 493 Kb, File published: Jan 14, 2002
Live-insertion capability is an essential part of today?s high-speed data systems because those systems are expected to run continuously without being powered down. This application report delves into the cause and prevention of live-insertion and nanosecond-discontinuity effects, using both simulation and actual test measurements from a specially built GTLP EVM. Hypothetical cases for precharge c
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Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
PDF, 585 Kb, File published: Apr 5, 2001
This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).The basic characteristics of lines, key factors that influence the bus line delay, and the impedance of bus lines are described.The theoretical
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Fast GTLP Backplanes With the GTLPH1655 (Rev. A)
PDF, 1.1 Mb, Revision: A, File published: Sep 19, 2000
This revision of the Fast GTL Backplanes With the GTL1655 application report addresses improvements, such as the improved OECE circuitry and implementation of theTexas Instruments TI-OPCE circuitry, that have been incorporated in the GTLPH1655 device. These improvements significantly improve signal integrity in distributed loads.This application report describes the physical principles of fast
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Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
PDF, 209 Kb, File published: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

Model Line

Series: SN74GTLP1395 (3)

SN74GTLP1395DWR SN74GTLP1395PW SN74GTLP1395PWR

Manufacturer's Classification

Semiconductors > Logic > Backplane Logic (GTL/TTL/BTL/ECL Transceiver/Translator)