Datasheet Texas Instruments SN74GTLP1395

Manufacturer	Texas Instruments
Series	SN74GTLP1395

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Parametrics

Parameters / Models	SN74GTLP1395DWR	SN74GTLP1395PW	SN74GTLP1395PWR
Bits	2	2	2
F @ Nom Voltage(Max), Mhz	175	175	175
ICC @ Nom Voltage(Max), mA	20	20	20
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	100	100	100
Package Group	SOIC	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Rating	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No
Technology Family	GTLP	GTLP	GTLP
VCC(Max), V	3.45	3.45	3.45
VCC(Min), V	3.15	3.15	3.15
Voltage(Nom), V	3.3	3.3	3.3
tpd @ Nom Voltage(Max), ns	9.7	9.7	9.7

Eco Plan

Application Notes

• Download
  Texas Instruments GTLP Frequently Asked Questions
  PDF, 496 Kb, File published: Jan 1, 2001
  Using a question-and-answer format, advantages of TI?s GTLP devices, particularly for backplane applications, are presented, as well as differences between GTLP and GTL/LVDS devices. Applicable topics include data throughput rates, synchronous clocks, price and alternative sources, bus transceivers, live insertion, power consumption, backplane termination, voltage translation, IBIS and HSPICE mode
• Download
  Logic in Live-Insertion Applications With a Focus on GTLP
  PDF, 493 Kb, File published: Jan 14, 2002
  Live-insertion capability is an essential part of today?s high-speed data systems because those systems are expected to run continuously without being powered down. This application report delves into the cause and prevention of live-insertion and nanosecond-discontinuity effects, using both simulation and actual test measurements from a specially built GTLP EVM. Hypothetical cases for precharge c
• Download
  Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
  PDF, 585 Kb, File published: Apr 5, 2001
  This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).The basic characteristics of lines, key factors that influence the bus line delay, and the impedance of bus lines are described.The theoretical
• Download
  Fast GTLP Backplanes With the GTLPH1655 (Rev. A)
  PDF, 1.1 Mb, Revision: A, File published: Sep 19, 2000
  This revision of the Fast GTL Backplanes With the GTL1655 application report addresses improvements, such as the improved OECE circuitry and implementation of theTexas Instruments TI-OPCE circuitry, that have been incorporated in the GTLPH1655 device. These improvements significantly improve signal integrity in distributed loads.This application report describes the physical principles of fast
• Download
  Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
  PDF, 209 Kb, File published: May 10, 2002
  Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

Model Line

Manufacturer's Classification

• Semiconductors> Logic> Backplane Logic (GTL/TTL/BTL/ECL Transceiver/Translator)