Datasheet Texas Instruments SN74LVT125

ManufacturerTexas Instruments
SeriesSN74LVT125
Datasheet Texas Instruments SN74LVT125

3.3-V ABT Quadruple Bus Buffers With 3-State Outputs

Datasheets

SN74LVT125 datasheet
PDF, 673 Kb, Revision: F, File published: Oct 13, 2003
Extract from the document

Prices

Status

SN74LVT125DSN74LVT125DBLESN74LVT125DBRSN74LVT125DBRG4SN74LVT125DG4SN74LVT125DRSN74LVT125DRG4SN74LVT125NSRSN74LVT125PWSN74LVT125PWG4SN74LVT125PWLESN74LVT125PWRSN74LVT125PWRG4
Lifecycle StatusNRND (Not recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)NRND (Not recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)NRND (Not recommended for new designs)NRND (Not recommended for new designs)NRND (Not recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoYesNoNoNoNo

Packaging

SN74LVT125DSN74LVT125DBLESN74LVT125DBRSN74LVT125DBRG4SN74LVT125DG4SN74LVT125DRSN74LVT125DRG4SN74LVT125NSRSN74LVT125PWSN74LVT125PWG4SN74LVT125PWLESN74LVT125PWRSN74LVT125PWRG4
N12345678910111213
Pin14141414141414141414141414
Package TypeDDBDBDBDDDNSPWPWPWPWPW
Industry STD TermSOICSSOPSSOPSSOPSOICSOICSOICSOPTSSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY502000200050250025002000909020002000
CarrierTUBELARGE T&RLARGE T&RTUBELARGE T&RLARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&R
Device MarkingLVT125LX125LX125LVT125LVT125LVT125LVT125LX125LX125LX125LX125
Width (mm)3.915.35.35.33.913.913.915.34.44.44.44.44.4
Length (mm)8.656.26.26.28.658.658.6510.355555
Thickness (mm)1.581.951.951.951.581.581.581.9511111
Pitch (mm)1.27.65.65.651.271.271.271.27.65.65.65.65.65
Max Height (mm)1.752221.751.751.7521.21.21.21.21.2
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / ModelsSN74LVT125D
SN74LVT125D
SN74LVT125DBLE
SN74LVT125DBLE
SN74LVT125DBR
SN74LVT125DBR
SN74LVT125DBRG4
SN74LVT125DBRG4
SN74LVT125DG4
SN74LVT125DG4
SN74LVT125DR
SN74LVT125DR
SN74LVT125DRG4
SN74LVT125DRG4
SN74LVT125NSR
SN74LVT125NSR
SN74LVT125PW
SN74LVT125PW
SN74LVT125PWG4
SN74LVT125PWG4
SN74LVT125PWLE
SN74LVT125PWLE
SN74LVT125PWR
SN74LVT125PWR
SN74LVT125PWRG4
SN74LVT125PWRG4
Approx. Price (US$)0.52 | 1ku0.52 | 1ku
Bits44444444444
Bits(#)44
F @ Nom Voltage(Max), Mhz100100100100100100100100100100100
F @ Nom Voltage(Max)(Mhz)100100
ICC @ Nom Voltage(Max), mA0.0070.0070.0070.0070.0070.0070.0070.0070.0070.0070.007
ICC @ Nom Voltage(Max)(mA)0.0070.007
Input TypeTTL/CMOSTTL/CMOS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64
Output Drive (IOL/IOH)(Max)(mA)-32/64-32/64
Output TypeLVTTLLVTTL
Package GroupSOICSSOPSSOPSSOPSOICSOICSOICSOIC,SSOP,TSSOPTSSOPTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG14SOIC: 52 mm2: 6 x 8.65(SOIC)14SSOP: 48 mm2: 7.8 x 6.2(SSOP)14SSOP: 48 mm2: 7.8 x 6.2(SSOP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC),14SSOP: 48 mm2: 7.8 x 6.2(SSOP),14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Package Size: mm2:W x L (PKG)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.63.63.63.63.6
VCC(Max)(V)3.63.6
VCC(Min), V2.72.72.72.72.72.72.72.72.72.72.7
VCC(Min)(V)2.72.7
Voltage(Nom), V3.33.33.33.33.33.33.33.33.33.33.3
Voltage(Nom)(V)3.33.3
tpd @ Nom Voltage(Max), ns44444444444
tpd @ Nom Voltage(Max)(ns)44

Eco Plan

SN74LVT125DSN74LVT125DBLESN74LVT125DBRSN74LVT125DBRG4SN74LVT125DG4SN74LVT125DRSN74LVT125DRG4SN74LVT125NSRSN74LVT125PWSN74LVT125PWG4SN74LVT125PWLESN74LVT125PWRSN74LVT125PWRG4
RoHSCompliantNot CompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantNot CompliantCompliantCompliant
Pb FreeNoNo

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, File published: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Model Line

Manufacturer's Classification

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver