Datasheet Texas Instruments SN74LVT8980ADW

ManufacturerTexas Instruments
SeriesSN74LVT8980A
Part NumberSN74LVT8980ADW
Datasheet Texas Instruments SN74LVT8980ADW

Embedded Test-Bus Controllers IEEE STD 1149.1 (JTAG) TAP Masters W/ 8-Bit Generic Host Interfaces 24-SOIC -40 to 85

Datasheets

SN54LVT8980A, SN74LVT8980A datasheet
PDF, 865 Kb, Revision: B, File published: Mar 18, 2004
Extract from the document

Prices

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

Pin24
Package TypeDW
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Package QTY25
CarrierTUBE
Device MarkingLVT8980A
Width (mm)7.5
Length (mm)15.4
Thickness (mm)2.35
Pitch (mm)1.27
Max Height (mm)2.65
Mechanical DataDownload

Parametrics

Bits8
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)64/-32 mA
Package GroupSOIC
Package Size: mm2:W x L24SOIC: 160 mm2: 10.3 x 15.5(SOIC) PKG
RatingCatalog
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
tpd @ Nom Voltage(Max)30 ns

Eco Plan

RoHSCompliant

Application Notes

  • Programming CPLDs Via the 'LVT8986 LASP
    PDF, 819 Kb, File published: Nov 1, 2005
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, File published: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Model Line

Manufacturer's Classification

  • Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic