Datasheet Texas Instruments SN74LVT8986
| Manufacturer | Texas Instruments |
| Series | SN74LVT8986 |
3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) Tap Transceiver
Datasheets
3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG datasheet
PDF, 905 Kb, Revision: E, File published: May 14, 2007
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Status
| SN74LVT8986PM | SN74LVT8986ZGV | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | Yes |
Packaging
| SN74LVT8986PM | SN74LVT8986ZGV | |
|---|---|---|
| N | 1 | 2 |
| Pin | 64 | 64 |
| Package Type | PM | ZGV |
| Industry STD Term | LQFP | BGA MICROSTAR |
| JEDEC Code | S-PQFP-G | S-PBGA-N |
| Package QTY | 160 | 348 |
| Carrier | JEDEC TRAY (10+1) | JEDEC TRAY (5+1) |
| Device Marking | LVT8986 | LVT8986 |
| Width (mm) | 10 | 8 |
| Length (mm) | 10 | 8 |
| Thickness (mm) | 1.4 | .9 |
| Pitch (mm) | .5 | .8 |
| Max Height (mm) | 1.6 | 1.4 |
| Mechanical Data | Download | Download |
Eco Plan
| SN74LVT8986PM | SN74LVT8986ZGV | |
|---|---|---|
| RoHS | Compliant | Compliant |
Application Notes
- Cascading Multiple Linking Addressable Scan Port DevicesPDF, 216 Kb, File published: Nov 5, 2002
This application report is intended to illustrate the capability of cascading multiple Texas Instruments (TI) linking addressable scan port (LASP) devices. It explains configuring the secondary test access ports (TAPs) of cascaded LASPs with the help of a single linking shadow protocol and protocol-bypass inputs. Several examples of linking shadow protocol, along with timing requirements and scan - Programming CPLDs Via the 'LVT8986 LASPPDF, 819 Kb, File published: Nov 1, 2005
This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to - LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, File published: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Model Line
Series: SN74LVT8986 (2)
Manufacturer's Classification
- Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic
