Datasheet Texas Instruments SN74LVT8996

Manufacturer	Texas Instruments
Series	SN74LVT8996

3.3-V ABT 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) TAP Transceiver

Datasheets

PDF, 1.3 Mb, Revision: A, File published: Dec 2, 1999

Extract from the document

	SN74LVT8996DW	SN74LVT8996DWR	SN74LVT8996PW	SN74LVT8996PWR
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No

	SN74LVT8996DW	SN74LVT8996DWR	SN74LVT8996PW	SN74LVT8996PWR
N	1	2	3	4
Pin	24	24	24	24
Package Type	DW	DW	PW	PW
Industry STD Term	SOIC	SOIC	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	25	2000	60	2000
Carrier	TUBE	LARGE T&R	TUBE	LARGE T&R
Device Marking	LVT8996	LVT8996	LX8996	LX8996
Width (mm)	7.5	7.5	4.4	4.4
Length (mm)	15.4	15.4	7.8	7.8
Thickness (mm)	2.35	2.35	1	1
Pitch (mm)	1.27	1.27	.65	.65
Max Height (mm)	2.65	2.65	1.2	1.2
Mechanical Data	Download	Download	Download	Download

Parameters / Models	SN74LVT8996DW	SN74LVT8996DWR	SN74LVT8996PW	SN74LVT8996PWR
Bits	10	10	10	10
ICC @ Nom Voltage(Max), mA	20	20	20	20
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	64/-32	64/-32	64/-32	64/-32
Package Group	SOIC	SOIC	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	24SOIC: 160 mm2: 10.3 x 15.5(SOIC)	24SOIC: 160 mm2: 10.3 x 15.5(SOIC)	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog
Technology Family	LVT	LVT	LVT	LVT
VCC(Max), V	3.6	3.6	3.6	3.6
VCC(Min), V	2.7	2.7	2.7	2.7

	SN74LVT8996DW	SN74LVT8996DWR	SN74LVT8996PW	SN74LVT8996PWR
RoHS	Compliant	Compliant	Compliant	Compliant

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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, File published: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Series: SN74LVT8996 (4)