Datasheet Texas Instruments CLVTH162373MDLREP

Manufacturer	Texas Instruments
Series	SN74LVTH162373-EP
Part Number	CLVTH162373MDLREP

Enhanced Product 3.3-V Abt 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -55 to 125

Datasheets

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PDF, 279 Kb, Revision: A, File published: Jul 13, 2006

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Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Packaging

Pin	48
Package Type	DL
Industry STD Term	SSOP
JEDEC Code	R-PDSO-G
Package QTY	1000
Carrier	LARGE T&R
Device Marking	LVTH162373MEP
Width (mm)	7.49
Length (mm)	15.88
Thickness (mm)	2.59
Pitch (mm)	.635
Max Height (mm)	2.79
Mechanical Data	Download

Parametrics

3-State Output	Yes
Bits	16
F @ Nom Voltage(Max)	160 Mhz
ICC @ Nom Voltage(Max)	5 mA
Input Type	TTL
Operating Temperature Range	-55 to 125 C
Output Drive (IOL/IOH)(Max)	12/-12 mA
Output Type	TTL
Package Group	SSOP
Package Size: mm2:W x L	48SSOP: 164 mm2: 10.35 x 15.88(SSOP) PKG
Rating	HiRel Enhanced Product
Technology Family	LVT
VCC(Max)	3.6 V
VCC(Min)	2.7 V
tpd @ Nom Voltage(Max)	4.6 ns

Eco Plan

RoHS

Compliant

Application Notes

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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, File published: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, Revision: B, File published: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
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Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
PDF, 105 Kb, Revision: A, File published: Aug 1, 1997
The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
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Understanding Advanced Bus-Interface Products Design Guide
PDF, 253 Kb, File published: May 1, 1996
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Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
PDF, 209 Kb, File published: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
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Power-Up Behavior of Clocked Devices (Rev. A)
PDF, 34 Kb, Revision: A, File published: Feb 6, 2015

Model Line

Series: SN74LVTH162373-EP (2)

CLVTH162373MDLREP V62/06654-01XE

Manufacturer's Classification

Semiconductors > Space & High Reliability > Logic Products > Flip-Flop/Latch/Registers