Datasheet Texas Instruments SN74LVTH32374

ManufacturerTexas Instruments
SeriesSN74LVTH32374
Datasheet Texas Instruments SN74LVTH32374

3.3-V ABT 32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs

Datasheets

SN74LVTH32374 datasheet
PDF, 728 Kb, Revision: D, File published: Aug 10, 2007
Extract from the document

Prices

Status

SN74LVTH32374ZKER
Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

Packaging

SN74LVTH32374ZKER
N1
Pin96
Package TypeZKE
Industry STD TermBGA MICROSTAR
JEDEC CodeR-PBGA-N
Package QTY1000
CarrierLARGE T&R
Device MarkingHV374
Width (mm)5.5
Length (mm)13.5
Thickness (mm).85
Pitch (mm).8
Max Height (mm)1.4
Mechanical DataDownload

Parametrics

Parameters / ModelsSN74LVTH32374ZKER
SN74LVTH32374ZKER
3-State OutputYes
Bits32
F @ Nom Voltage(Max), Mhz160
ICC @ Nom Voltage(Max), mA10
Operating Temperature Range, C-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-32
Package GroupLFBGA
Package Size: mm2:W x L, PKG96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA)
RatingCatalog
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max), V3.6
VCC(Min), V2.7
Voltage(Nom), V3.3
tpd @ Nom Voltage(Max), ns4.5

Eco Plan

SN74LVTH32374ZKER
RoHSCompliant

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, File published: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, File published: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Model Line

Series: SN74LVTH32374 (1)

Manufacturer's Classification

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop