Datasheet Texas Instruments SN75LVDS82DGGG4
Manufacturer | Texas Instruments |
Series | SN75LVDS82 |
Part Number | SN75LVDS82DGGG4 |
FlatLink Receiver 56-TSSOP 0 to 70
Datasheets
SN75LVDS82 FlatLinkв„ў Receiver datasheet
PDF, 1.5 Mb, Revision: J, File published: Oct 24, 2016
Extract from the document
Prices
Status
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Packaging
Pin | 56 |
Package Type | DGG |
Industry STD Term | TSSOP |
JEDEC Code | R-PDSO-G |
Package QTY | 35 |
Carrier | TUBE |
Device Marking | SN75LVDS82 |
Width (mm) | 6.1 |
Length (mm) | 14 |
Thickness (mm) | 1.15 |
Pitch (mm) | .5 |
Max Height (mm) | 1.2 |
Mechanical Data | Download |
Parametrics
Operating Temperature Range | 0 to 70 C |
Package Group | TSSOP |
Package Size: mm2:W x L | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) PKG |
Protocols | Channel-Link I |
Rating | Catalog |
Supply Voltage(s) | 3.3 V |
Eco Plan
RoHS | Compliant |
Application Notes
- FlatLinkв„ў Data Transmission System Using SN75LVDS83B/SN75LVDS82/SN75LVDS86APDF, 333 Kb, File published: Feb 2, 2010
This application report presents various system designs possible using the FlatLinkв„ў transmitter:SN75LVDS83B, and the FlatLinkв„ў receivers: SN75LVDS82 and SN75LVDS86A. These are low-voltagedifferential signaling (LVDS) serializer/deserializer (SerDes) devices commonly used to transmit video datato liquid crystal display (LCD) panels. The application report starts with an introduction of the F - Time Budgeting of the Flatlink Interface Application ReportPDF, 99 Kb, File published: Jun 11, 1997
This document describes the FlatLinkE point-to-point data-transmission interface that provides better than a two-to-one reduction in the number of signal lines used for synchronous parallel data-bus structures. - Flatlink Data Transmission System Design Overview (Rev. A)PDF, 127 Kb, Revision: A, File published: Jun 1, 2001
FlatLink is a data transmission system that can provide better than a 2:1 reduction in the number of signal lines used for synchronous parallel data bus structures with no loss in data throughput. To do this, FlatLink takes single-ended data at clock rates of up to 68 MHz and increases the data signaling rate seven times up to 476 Mbps. The following report provides some design guidelinesfo
Model Line
Series: SN75LVDS82 (4)
- SN75LVDS82DGG SN75LVDS82DGGG4 SN75LVDS82DGGR SN75LVDS82DGGRG4
Manufacturer's Classification
- Semiconductors > Interface > LVDS/M-LVDS/PECL > SerDes/Channel-Link