This guide describes the main System-on-Chip (SoC) level and peripheral changes that need to be considered when migrating a KeyStone I-based system design to a KeyStone II-based system design.In this guide, KeyStone I includes all TMS320TCI661x devices and KeyStone II includes all TCI663xK2y devices. Any differences within KeyStone I or KeyStone II devices are described explicitly.
PDF, 154 Kb, File published: Sep 18, 2015
This application report describes an application circuit example of the TPS544B/Cxx family of power management IC (PMIC) powering the Smart-Reflex digital core supply of the TCI6630K2L SoC. Smart-Reflex Class 0 Temperature Compensation (Class 0 TC) mode of operation of the TCI6630K2L device is emphasized. Assumption is that temperature compensation mode is enabled using the function provided in th
PDF, 866 Kb, Revision: B, File published: Dec 22, 2015
This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access.
PDF, 143 Kb, File published: Oct 16, 2015
This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device.
PDF, 73 Kb, File published: Jan 26, 2015
This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller.
PDF, 61 Kb, Revision: C, File published: Jul 15, 2016
This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices.
PDF, 1.8 Mb, File published: Mar 24, 2014
PDF, 138 Kb, File published: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
PDF, 320 Kb, File published: Dec 13, 2011
PDF, 585 Kb, File published: Nov 9, 2010
PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
PDF, 1.5 Mb, File published: Nov 9, 2010
PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
PDF, 324 Kb, Revision: A, File published: Aug 17, 2016
This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require
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Manufacturer's Classification
- Semiconductors> Processors> Communications Processors> TCI66x
