Datasheet Texas Instruments TCI6638K2K
Manufacturer | Texas Instruments |
Series | TCI6638K2K |
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
Datasheets
TCI6638K2K Multicore DSP+ARMВ® KeyStone II System-on-Chip (SoC) datasheet
PDF, 2.2 Mb, Revision: F, File published: May 5, 2017
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Status
TCI6638K2KBXAAW2 | |
---|---|
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Packaging
TCI6638K2KBXAAW2 | |
---|---|
N | 1 |
Pin | 1517 |
Package Type | AAW |
Package QTY | 21 |
Carrier | JEDEC TRAY (5+1) |
Device Marking | @2012 TI |
Width (mm) | 40 |
Length (mm) | 40 |
Thickness (mm) | 3.07 |
Mechanical Data | Download |
Eco Plan
TCI6638K2KBXAAW2 | |
---|---|
RoHS | Compliant |
Application Notes
- Ethernet Packet Transfer Via FastC&M over AIF2 Application ReportPDF, 168 Kb, File published: Dec 6, 2013
- KeyStone I-to-KeyStone II Migration Guide (Rev. A)PDF, 479 Kb, Revision: A, File published: Jul 30, 2015
This guide describes the main System-on-Chip (SoC) level and peripheral changes that need to be considered when migrating a KeyStone I-based system design to a KeyStone II-based system design.In this guide, KeyStone I includes all TMS320TCI661x devices and KeyStone II includes all TCI663xK2y devices. Any differences within KeyStone I or KeyStone II devices are described explicitly.Keystone II DDR3 InitializationPDF, 73 Kb, File published: Jan 26, 2015
This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller.Throughput Performance Guide for KeyStone II Devices (Rev. B)PDF, 866 Kb, Revision: B, File published: Dec 22, 2015
This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access.Keystone II DDR3 Debug GuidePDF, 143 Kb, File published: Oct 16, 2015
This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device.Power Management of KS2 Device (Rev. C)PDF, 61 Kb, Revision: C, File published: Jul 15, 2016
This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices.Hardware Design Guide for KeyStone II DevicesPDF, 1.8 Mb, File published: Mar 24, 2014SERDES Link Commissioning on KeyStone I and II DevicesPDF, 138 Kb, File published: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.PCIe Use Cases for KeyStone DevicesPDF, 320 Kb, File published: Dec 13, 2011Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, File published: Nov 9, 2010Optimizing Loops on the C66x DSPPDF, 585 Kb, File published: Nov 9, 2010The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROMDDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, Revision: B, File published: Jun 5, 2014Multicore Programming Guide (Rev. B)PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicoreThermal Design Guide for DSP and ARM Application Processors (Rev. A)PDF, 324 Kb, Revision: A, File published: Aug 17, 2016
This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal requireModel Line
Series: TCI6638K2K (1)Manufacturer's Classification
- Semiconductors> Processors> Other Processors