Datasheet Texas Instruments TMS320C6652

Manufacturer	Texas Instruments
Series	TMS320C6652

Datasheets

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Packaging

Parametrics

Parameters / Models	TMS320C6652CZH6	TMS320C6652CZHA6
Applications	Machine Vision	Machine Vision
DRAM	DDR3	DDR3
DSP	1 C66x	1 C66x
DSP MHz, Max.	600	600
GFLOPS	9.6	9.6
On-Chip L2 Cache	1024 KB	1024 KB
Operating Temperature Range, C	-40 to 100,0 to 85	-40 to 100,0 to 85
Other On-Chip Memory	1024 KB	1024 KB
Package Size: mm2:W x L, PKG	See datasheet (FCBGA)	See datasheet (FCBGA)
Rating	Catalog	Catalog
Serial I/O	I2C,SPI,UART,UPP	I2C,SPI,UART,UPP
Total On-Chip Memory, KB	1088	1088

Eco Plan

Application Notes

• Download
  Hardware Design Guide for KeyStone Devices (Rev. C)
  PDF, 1.7 Mb, Revision: C, File published: Sep 15, 2013
• Download
  TMS320C66x DSP Generation of Devices (Rev. A)
  PDF, 245 Kb, Revision: A, File published: Apr 25, 2011
• Download
  KeyStone I DDR3 Initialization (Rev. E)
  PDF, 114 Kb, Revision: E, File published: Oct 28, 2016
  The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
• Download
  AN-1281 Bumped Die (Flip Chip) Packages (Rev. A)
  PDF, 2.2 Mb, Revision: A, File published: May 1, 2004
  Application Note 1281 Bumped Die (Flip Chip) Packages
• Download
  Clocking Design Guide for KeyStone Devices
  PDF, 1.5 Mb, File published: Nov 9, 2010
• Download
  The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
  PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
  The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
• Download
  Optimizing Loops on the C66x DSP
  PDF, 585 Kb, File published: Nov 9, 2010
• Download
  DDR3 Design Requirements for KeyStone Devices (Rev. B)
  PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
• Download
  TI DSP Benchmarking
  PDF, 62 Kb, File published: Jan 13, 2016
  This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.
• Download
  Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
  PDF, 324 Kb, Revision: A, File published: Aug 17, 2016
  This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require
• Download
  Plastic Ball Grid Array [PBGA] Application Note (Rev. B)
  PDF, 1.6 Mb, Revision: B, File published: Aug 13, 2015

Model Line

Manufacturer's Classification

• Semiconductors> Processors> Digital Signal Processors> C6000 DSP> C66x DSP