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Design Notes

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  A Robust 10MHz Reference Clock Input Protection Circuit and Distributor for RF Systems &mdash DN514
  PDF, 420 Kb, File published: Apr 9, 2013
  Extract from the document

  advertisement A Robust 10MHz Reference Clock Input Protection Circuit and
  Distributor for RF Systems – Design Note 514
  Michel Azarian
  Introduction
  Designing the reference input circuit for an RF system
  can prove tricky. One challenge is maintaining the phase
  noise performance of the input clock while meeting the
  protection, buffering and distribution requirements for
  the clock. This article shows how to design a 10MHz
  reference input circuit and optimize its performance.
  Design Requirements
  RF instruments and wireless transceivers often feature
  an input for an external reference clock, such as the
  ubiquitous 10MHz reference input port found on RF
  instruments. Many of these same systems include a
  provision to distribute the reference clock through the
  system. Figure 1 shows a common scheme, where
  the reference clock supplies the reference input to two
  distinct phase-locked loops (PLLs).
  A well-designed, robust input would accept both sine
  and square wave signals over a wide range of amplitudes. It would maintain a constant signal level drive
  to the destination PLL inputs inside the system, even
  in the face of varied inputs. The exposed-to-the-world …

Articles

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  Reference Clock Distribution for a 325MHz IF Sampling System with over 30MHz Bandwidth, 64dB SNR and 80dB SFDR &mdash LT Journal
  PDF, 2.8 Mb, File published: Jul 9, 2013
  Extract from the document

  Reference Clock Distribution for a 325MHz IF
  Sampling System with over 30MHz Bandwidth,
  64dB SNR and 80dB SFDR
  Michel Azarian Clock jitter introduced in an RF receiver through reference
  clock buffering and distribution can limit achievable system
  performance. The low jitter requirement is further exaggerated
  when a relatively high intermediate frequency (IF) is used
  in an effort to reap the benefits of relaxed front-end filter
  requirements. This article details the design of a 325MHz
  IF sampling system and introduces a clock buffer and
  distributor that converts a sine wave reference signal into a
  pair of differential LVPECL clocks appropriate to drive high
  speed ADCs, and does so while minimizing introduced jitter.
  SYSTEM DESCRIPTION In an IF sampling (or undersampling)
  system, where the ADC performs the last
  stage of downconversion in an RF receiver,
  the higher the IF is, the less steep the
  image rejection filter in the RF front-end
  can be. This helps in reducing the filter cost, size and insertion loss, which
  further lessens the need for amplification,
  leading to even lower cost and power
  consumption. Figure 1 shows a typical
  RF receiver chain employing IF sampling. …

Model Line

Manufacturer's Classification

• Signal Conditioning > Comparators > High Speed Comparators
• Timing > Clock Generation and Distribution > Clock Distribution
• Timing > Extended Temperature (H & MP) Timing

Other Names:

LTC6957IDD-4PBF, LTC6957IDD-4 PBF, LTC6957IDD4#PBF, LTC6957IDD 4#PBF