Datasheet Analog Devices 5962-8859301M2A

REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change to one part-one part number format. Added table III. 91-12-11 M. A. FRYE B Changes in accordance with NOR 5962-R036-97. 96-11-26 R. MONNIN C Change slew rate value in table I. Remove table III, figures 2, 3, 4, and 5.
Update boilerplate. Redrawn. -rrp 00-10-18 R. MONNIN D Replaced reference to MIL-STD-973 with reference to MIL-PRF-38535. -rrp 03-05-01 R. MONNIN E Make change to the AVS, +VOP, and -VOP test subgroups from 4, 5, and 6 to 11-05-10 C. SAFFLE 1, 2, and 3 as specified under table I. Make change to the En and SR test
subgroups from 7 to 4 as specified under table I. Make change to TCVIO test
subgroups from 8 to 2 and 3 under table I. Make change to paragraph 4.4.1
and table IIA. Update drawing to current requirements. -rrp
F Update drawing to current MIL-PRF-38535 requirements. -rrp 16-10-06 C. SAFFLE THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.
REV
SHEET
REV
SHEET
REV STATUS REV F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY
GARY ZAHN STANDARD
MICROCIRCUIT
DRAWING DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil CHECKED BY
RAY MONNIN
APPROVED BY THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE AMSC N/A D. A. DiCENZO …

Dual Low Offset, Low Power
Operational Amplifier
OP200 Data Sheet PIN CONNECTIONS Low input offset voltage: 75 μV maximum
Low offset voltage drift, over −55°C < TA < +125°C
0.5 μV/°C maximum
Low supply current (per amplifier): 725 μA maximum
High open-loop gain: 5000 V/mV minimum
Low input bias current: 2 nA maximum
Low noise voltage density: 11 nV/√Hz at 1 kHz
Stable with large capacitive loads: 10 nF typical –IN A 1 16 OUT A +IN A 2 15 NC NC 3 14 NC V– 4 13 V+ NC 5 12 NC +IN B 6 11 NC –IN B 7 10 OUT B NC 8 9 NC NC = NO CONNECT 00322-001 FEATURES OUT A 1 –IN A 2 +IN A 3 V– 4 OP200
A
B 8 V+ 7 OUT B 6 –IN B 5 +IN B 00322-002 Figure 1. 16-Lead SOIC (S-Suffix) Figure 2. 8-Lead PDIP (P-Suffix)
8-Lead CERDIP (Z-Suffix) GENERAL DESCRIPTION
The OP200 is the first monolithic dual operational amplifier
to offer OP77 type precision performance. Available in the
industry standard 8-lead pinout, the OP200 combines precision
performance with the space and cost savings offered by a dual
amplifier.
The OP200 features an extremely low input offset voltage of
less than 75 μV with a drift below 0.5 μV/°C, guaranteed over
the full military temperature range. Open-loop gain of the OP200
exceeds 5,000,000 into a 10 kΩ load; input bias current is under
2 nA; CMRR is over 120 dB; and PSRR is below 1.8 μV/V. On-chip …

Dual Low Offset, Low Power
Operational Amplifier
OP200 Data Sheet PIN CONNECTIONS Low input offset voltage: 75 μV maximum
Low offset voltage drift, over −55°C < TA < +125°C
0.5 μV/°C maximum
Low supply current (per amplifier): 725 μA maximum
High open-loop gain: 5000 V/mV minimum
Low input bias current: 2 nA maximum
Low noise voltage density: 11 nV/√Hz at 1 kHz
Stable with large capacitive loads: 10 nF typical –IN A 1 16 OUT A +IN A 2 15 NC NC 3 14 NC V– 4 13 V+ NC 5 12 NC +IN B 6 11 NC –IN B 7 10 OUT B NC 8 9 NC NC = NO CONNECT 00322-001 FEATURES OUT A 1 –IN A 2 +IN A 3 V– 4 OP200
A
B 8 V+ 7 OUT B 6 –IN B 5 +IN B 00322-002 Figure 1. 16-Lead SOIC (S-Suffix) Figure 2. 8-Lead PDIP (P-Suffix)
8-Lead CERDIP (Z-Suffix) GENERAL DESCRIPTION
The OP200 is the first monolithic dual operational amplifier
to offer OP77 type precision performance. Available in the
industry standard 8-lead pinout, the OP200 combines precision
performance with the space and cost savings offered by a dual
amplifier.
The OP200 features an extremely low input offset voltage of
less than 75 μV with a drift below 0.5 μV/°C, guaranteed over
the full military temperature range. Open-loop gain of the OP200
exceeds 5,000,000 into a 10 kΩ load; input bias current is under
2 nA; CMRR is over 120 dB; and PSRR is below 1.8 μV/V. On-chip …