Datasheet Texas Instruments 66AK2H14DAAWA24

ManufacturerTexas Instruments
Series66AK2H14
Part Number66AK2H14DAAWA24
Datasheet Texas Instruments 66AK2H14DAAWA24

Multicore DSP+ARM KeyStone II System-on-Chip (SoC) 1517-FCBGA -40 to 100

Datasheets

66AK2Hxx Multicore DSP+ARMВ® KeyStone II System-on-Chip (SoC) datasheet
PDF, 2.4 Mb, Revision: F, File published: Jun 2, 2017
Extract from the document

Prices

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

Pin151715171517
Package TypeAAWAAWAAW
Package QTY212121
CarrierJEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)
Device MarkingA1.2GHZ/1.4GHZ66AK2H14AAW@2012 TI
Width (mm)404040
Length (mm)404040
Thickness (mm)3.073.073.07
Mechanical DataDownloadDownloadDownload

Parametrics

ARM CPU4 ARM Cortex-A15
ARM MHz1200,1400 Max.
ApplicationsAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space
DRAMDDR3,DDR3L
DSP8 C66x
DSP MHz1200 Max.
EMAC10G Ethernet
Hardware AcceleratorsPacket Accelerator,Security Accelerator
I2C3
On-Chip L2 Cache4096 KB (ARM Cluster),1024 KB (per C66x DSP core)
Operating SystemsIntegrity,Linux,SYS/BIOS,VxWorks
Operating Temperature Range-40 to 100,0 to 85 C
Other On-Chip Memory6144 KB
PCI/PCIe2 PCIe Gen2
RatingCatalog
SPI3
UART2 SCI
USB1

Eco Plan

RoHSCompliant

Design Kits & Evaluation Modules

  • JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
    XDS560v2 System Trace USB Debug Probe
    Lifecycle Status: Active (Recommended for new designs)
  • JTAG Emulators/ Analyzers: TMDSEMU200-U
    XDS200 USB Debug Probe
    Lifecycle Status: Active (Recommended for new designs)
  • JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
    XDS560v2 System Trace USB & Ethernet Debug Probe
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: EVMK2H
    66AK2H Evaluation Modules
    Lifecycle Status: Active (Recommended for new designs)

Application Notes

  • PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)
    PDF, 57 Kb, Revision: A, File published: May 19, 2017
  • Keystone II DDR3 Initialization
    PDF, 73 Kb, File published: Jan 26, 2015
    This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller.
  • Throughput Performance Guide for KeyStone II Devices (Rev. B)
    PDF, 866 Kb, Revision: B, File published: Dec 22, 2015
    This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access.
  • Keystone II DDR3 Debug Guide
    PDF, 143 Kb, File published: Oct 16, 2015
    This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device.
  • Power Management of KS2 Device (Rev. C)
    PDF, 61 Kb, Revision: C, File published: Jul 15, 2016
    This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices.
  • Hardware Design Guide for KeyStone II Devices
    PDF, 1.8 Mb, File published: Mar 24, 2014
  • SERDES Link Commissioning on KeyStone I and II Devices
    PDF, 138 Kb, File published: Apr 13, 2016
    The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
  • PCIe Use Cases for KeyStone Devices
    PDF, 320 Kb, File published: Dec 13, 2011
  • The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
    PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
    The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
  • Clocking Design Guide for KeyStone Devices
    PDF, 1.5 Mb, File published: Nov 9, 2010
  • Optimizing Loops on the C66x DSP
    PDF, 585 Kb, File published: Nov 9, 2010
  • DDR3 Design Requirements for KeyStone Devices (Rev. B)
    PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
  • Multicore Programming Guide (Rev. B)
    PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
    As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
  • Processor SDK RTOS Audio Benchmark Starter Kit
    PDF, 530 Kb, File published: Apr 12, 2017
    The TI TMS320C6000в„ў Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications that are commonly used in audio processing application. This application notes describes Audio Benchmark Starterkit software that is intended to provide an easy and quick way to benchmark key audio functions on C66x and C674x DSP device
  • TI DSP Benchmarking
    PDF, 62 Kb, File published: Jan 13, 2016
    This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.

Model Line

Manufacturer's Classification

  • Semiconductors > Processors > Digital Signal Processors > C6000 DSP + ARM Processors > 66AK2x