Datasheet Texas Instruments 74SSTUB32865AZJBR
| Manufacturer | Texas Instruments |
| Series | 74SSTUB32865A |
| Part Number | 74SSTUB32865AZJBR |
28-Bit to 56-Bit Registered Buffer with Address-Parity Test 160-NFBGA -40 to 85
Datasheets
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST datasheet
PDF, 767 Kb, File published: Jul 25, 2007
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 160 |
| Package Type | ZJB |
| Industry STD Term | NFBGA |
| JEDEC Code | R-PBGA-N |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | SB865A |
| Width (mm) | 9 |
| Length (mm) | 13 |
| Thickness (mm) | .77 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | N/A ps |
| Function | DDR2 Register |
| Number of Outputs | 56 |
| Operating Frequency Range(Max) | 410 MHz |
| Operating Temperature Range | -40 to 85 C |
| Output Drive | 12 mA |
| Package Group | NFBGA |
| Package Size: mm2:W x L | 160NFBGA: 117 mm2: 9 x 13(NFBGA) PKG |
| Rating | Catalog |
| VCC | 1.8 V |
| t(phase error) | N/A ps |
| tsk(o) | N/A ps |
Eco Plan
| RoHS | Compliant |
Application Notes
- DDR2 Memory Interface Clocks and Registers - OverviewPDF, 308 Kb, File published: Mar 25, 2009
This application report gives an overview of the existing JEDEC DDR2 Register and PLL Buffer specifications and compliant TI devices.
Model Line
Series: 74SSTUB32865A (1)
- 74SSTUB32865AZJBR
Manufacturer's Classification
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers
