Datasheet Analog Devices AD8306ARZ-RL7

REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. – gt 03-02-10 R. MONNIN B Modify drawing to current requirements. -rrp 10-04-27 C. SAFFLE 12-04-25 C. SAFFLE 13-04-26 C. SAFFLE Add device type 02 and case outline X. Make changes to TJ, θJC, and θJA
under paragraph 1.3. Add enable input, limiter output current, minimum VLOG
output load resistance, differential input level, and single ended input level C limits under paragraph 1.3. Add a new footnote to θJC under paragraph 1.3.
Add paragraphs 1.4.1, 4.4.1c, 4.4.4.1, 6.7 and Table IIB. For device type 02,
add ILIM10, ILIM1, VIH, VIL, IIH, IIL, PIN, RIN, VLIM, FLIM, PINLIM, VLOGM, tSTL,
tRISE, and tFALL tests under Table I. -ro
D Add device type 03. Delete device class M references. -ro REV
SHEET
REV D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY
RICK OFFICER STANDARD
MICROCIRCUIT
DRAWING DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil CHECKED BY
RAJESH PITHADIA
APPROVED BY THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE AMSC N/A RAYMOND MONNIN
DRAWING APPROVAL DATE MICROCIRCUIT, LINEAR, LOGARITHMIC
AMPLIFIER, MONOLITHIC SILICON 99-04-26 …

a 5 MHz–400 MHz 100 dB High Precision
Limiting-Logarithmic Amplifier
AD8306 FEATURES
Complete, Fully Calibrated Log-Limiting IF Amplifier
100 dB Dynamic Range: –91 dBV to +9 dBV
Stable RSSI Scaling Over Temperature and Supplies:
20 mV/dB Slope, –95 dBm Intercept
ⴞ0.4 dB RSSI Linearity up to 200 MHz
Programmable Limiter Gain and Output Current
Differential Outputs to 10 mA, 2.4 V p-p
Overall Gain 90 dB, Bandwidth 400 MHz
Constant Phase (Typical ⴞ56 ps Delay Skew)
Single Supply of +2.7 V to +6.5 V at 16 mA Typical
Fully Differential Inputs, RIN = 1 k⍀, C IN = 2.5 pF
500 ns Power-Up Time, 4.5 V. For frequencies
in the range 10 MHz to 200 MHz these high drive levels are
easily achieved using a matching network. Using such a network, having an inductor at the input, the input transient is
eliminated. voltage sensitivity. Most interfaces have additional small junction capacitances associated with them, due to active devices or
ESD protection; these may be neither accurate nor stable.
Component numbering in each of these interface diagrams is
local.
Enable Interface The chip-enable interface is shown in Figure 20. The current in
R1 controls the turn-on and turn-off states of the band-gap …

a 5 MHz–400 MHz 100 dB High Precision
Limiting-Logarithmic Amplifier
AD8306 FEATURES
Complete, Fully Calibrated Log-Limiting IF Amplifier
100 dB Dynamic Range: –91 dBV to +9 dBV
Stable RSSI Scaling Over Temperature and Supplies:
20 mV/dB Slope, –95 dBm Intercept
ⴞ0.4 dB RSSI Linearity up to 200 MHz
Programmable Limiter Gain and Output Current
Differential Outputs to 10 mA, 2.4 V p-p
Overall Gain 90 dB, Bandwidth 400 MHz
Constant Phase (Typical ⴞ56 ps Delay Skew)
Single Supply of +2.7 V to +6.5 V at 16 mA Typical
Fully Differential Inputs, RIN = 1 k⍀, C IN = 2.5 pF
500 ns Power-Up Time, 4.5 V. For frequencies
in the range 10 MHz to 200 MHz these high drive levels are
easily achieved using a matching network. Using such a network, having an inductor at the input, the input transient is
eliminated. voltage sensitivity. Most interfaces have additional small junction capacitances associated with them, due to active devices or
ESD protection; these may be neither accurate nor stable.
Component numbering in each of these interface diagrams is
local.
Enable Interface The chip-enable interface is shown in Figure 20. The current in
R1 controls the turn-on and turn-off states of the band-gap …