Feature Summary 32-bit load/store RISC architecture
Up to 15 general-purpose 32-bit registers
32-bit Stack Pointer, Program Counter, and Link Register reside in register file
Fully orthogonal instruction set
Pipelined architecture allows one instruction per clock cycle for most instructions
Byte, half-word, word and double word memory access
Fast interrupts and multiple interrupt priority levels
Optional branch prediction for minimum delay branches
Privileged and unprivileged modes enabling efficient and secure Operating Systems
Innovative instruction set together with variable instruction length ensuring industry
leading code density
Optional DSP extention with saturated arithmetic, and a wide variety of multiply
instructions
Optional extensions for Java, SIMD, Read-Modify-Write to memory, and Coprocessors
Architectural support for efficient On-Chip Debug solutions
Optional MPU or MMU allows for advanced operating systems
FlashVaultв„ў support through Secure State for executing trusted code alongside
nontrusted code on the same CPU AVR32
Architecture
Document 32000D–04/2011 1. Introduction
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive
embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow for a variety of
microarchitectures, enabling the AVR32 to be implemented as low-, mid-or high-performance …
