Datasheet Microchip TP2104

ManufacturerMicrochip
SeriesTP2104

This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and well-proven, silicon-gate manufacturing process

Datasheets

TP2104 Datasheet - P-Channel Enhancement-Mode Vertical DMOS FET
PDF, 738 Kb, Revision: 06-27-2014
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Prices

Status

TP2104K1-GTP2104N3-GTP2104N3-G-P003
Lifecycle StatusProduction (Appropriate for new designs but newer alternatives may exist)Production (Appropriate for new designs but newer alternatives may exist)Production (Appropriate for new designs but newer alternatives may exist)

Packaging

TP2104K1-GTP2104N3-GTP2104N3-G-P003
N123
PackageSOT-23TO-92TO-92
Pins333

Parametrics

Parameters / ModelsTP2104K1-GTP2104N3-GTP2104N3-G-P003
BVdss min, V-40-40-40
CISSmax, pF606060
Operating Temperature Range, °C-55 to +150-55 to +150-55 to +150
Rds, on) max666
Vgs(th) max, V-2.0-2.0-2.0

Eco Plan

TP2104K1-GTP2104N3-GTP2104N3-G-P003
RoHSCompliantCompliantCompliant

Model Line