DATASHEET
KAD5512P FN6807
Rev 5.00
May 31, 2016 Low Power 12-Bit, 250/210/170/125MSPS ADC
The KAD5512P is the low-power member of the KAD5512
family of 12-bit analog-to-digital converters. Designed with
Intersil’s proprietary FemtoCharge™ technology on a standard
CMOS process, the family supports sampling rates of up to
250MSPS. The KAD5512P is part of a pin-compatible portfolio
of 10, 12 and 14-bit A/Ds with sample rates ranging from
125MSPS to 500MSPS. Features A Serial Peripheral Interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset. Over-range indicator Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512P is available in 72 Ld and 48 Ld QFN
packages with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C). Nap and sleep modes Key Specifications Single-supply 1.8V operation Half the power of the pin-compatible KAD5512HP family 1.5GHz analog input bandwidth 60fs clock jitter Programmable gain, offset and skew control Selectable clock divider: à 1, à 2 or à 4 Clock phase selection Two’s complement, gray code or binary data format SDR/DDR LVDS-compatible or LVCMOS outputs Programmable built-in test patterns Pb-free (RoHS compliant) SNR = 66.1dBFS for fIN = 105MHz (-1dBFS) Applications SFDR = 87dBc for fIN = 105MHz (-1dBFS) Total Power Consumption
-267/219mW at 250/125MSPS (SDR Mode)
-234/189mW at 250/125MSPS (DDR Mode) Power amplifier linearization Related Literature High-performance data acquisition Radar and satellite antenna array processing Broadband communications Communications test equipment KAD5512HP, Datasheet WiMAX and microwave receivers OVDD AVDD CLKDIV KAD5512P-50 Datasheet 0
CLKOUTP CLOCK
GENERATION CLKN D[11:0]P VINN
VCM AVSS NAPSLP 1.25V +
– SPI …
