DATASHEET
CD4027BMS FN3302
Rev 0.00
December 1992 CMOS Dual J-KMaster-Slave Flip-Flop Features Pinout High Voltage Type (20V Rating) CD4027BMS
TOP VIEW Set -Reset Capability Static Flip-Flop Operation -Retains State Indefinitely
with Clock Level Either “High” or “Low” Medium Speed Operation -16MHz (typ.) Clock Toggle
Rate at 10V Standardized Symmetrical Output Characteristics 100% Tested For Quiescent Current at 20V Maximum Input Current of 1пЃA at 18V Over Full
Package-Temperature Range;
-100nA at 18V and +25oC Noise Margin (Over Full Package Temperature Range):
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V 5V, 10V and 15V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
�B’ Series CMOS Devices” Q2 1 16 VDD Q2 2 15 Q1 CLOCK 2 3 14 Q1 RESET 2 4 13 CLOCK 1 K2 5 12 RESET 1 J2 6 11 K1 SET 2 7 10 J1
9 SET 1 VSS 8 Functional Diagram
SET 1 9 VDD
16 J1 10
K1 11
CLOCK1 13 15 Q1
F/F1 14 Q1 Applications Registers, Counters, Control Circuits Description
CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions for individual J, K,
Set Reset, and Clock input signals. Buffered Q and Q signals
are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CD4013B dual D …
