NOT RECOMMENDED FOR NEW DESIGNS
SY10E155
SY100E155
FINAL 6-BIT 2:1
MUX-LATCH
FEATURES DESCRIPTION
The SY10/100E155 offer six 2:1 multiplexers followed
by latches with single-ended outputs, designed for use in
new, high-performance ECL systems. The two external
latch-enable signals (LEN 1 and LEN2) are gated through a
logical OR operation before use as control for the six
latches. When both LEN1 and LEN 2 are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN 1 or LEN2 (or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the SEL (Select)
signal which selects one of the two bits of input data at each
mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW. 750ps max. LEN to output
Extended 100E VEE range of –4.2V to –5.5V
700ps max. D to output
Single-ended outputs …
