Features
• Utilizes the AVR® RISC Architecture
• AVR - High-performance and Low-power RISC Architecture • • • •
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• - 120 Powerful Instructions - Most Single Clock Cycle Execution
- 32 x 8 General Purpose Working Registers
- Fully Static Operation
- Up to 20 MIPS Throughput at 20 MHz
Data and Non-volatile Program and Data Memories
- 2K Bytes of In-System Self Programmable Flash
Endurance 10,000 Write/Erase Cycles
- 128 Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
- 128 Bytes Internal SRAM
- Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
- One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
- One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes
- Four PWM Channels
- On-chip Analog Comparator
- Programmable Watchdog Timer with On-chip Oscillator
- USI - Universal Serial Interface
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