Datasheet Analog Devices HMC6832ALP5LETR

Low Noise, 2:8 Differential
Fanout Buffer
HMC6832 Data Sheet
FEATURES GENERAL DESCRIPTION Ultralow noise floor: −165.9 dBc/Hz or −165.2 dBc/Hz
(LVPECL or LVDS) at 2000 MHz
Configurable to LVPECL or pseudo LVDS outputs
2.5 V or 3.3 V LVPECL operation (LVDS 2.5 V only)
Wideband: 10 MHz to 3500 MHz operating frequency range
Flexible input interface
LVPECL, LVDS, CML, and CMOS compatible
AC or dc coupling
On-chip 50 kΩ pull-up/pull-down resistors to VDD and
GND
Multiple output drivers
Up to 8 differential or 16 single-ended LVPECL or LVDS
outputs
Low speed digital control via the IN_SEL and CONFIG pins
28-lead, 5 mm × 5 mm, LFCSP package, 25 mm2 The HMC6832 is an input selectable, 2:8 differential fanout
buffer designed for low noise clock distribution. The IN_SEL
control pin selects one of the two differential inputs. This input
is then buffered to all eight differential outputs. The low jitter
outputs of the HMC6832 lead to synchronized low noise
switching of downstream circuits, such as mixers, analog-todigital converters (ADCs)/digital-to-analog converters (DACs), …