Datasheet NXP PMN50XP,165

PMN50XP
P-channel TrenchMOS extremely low level FET
Rev. 02 — 2 October 2007 Product data sheet 1. Product profile
1.1 General description
Extremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a
plastic package. This product is designed and qualified for use in computing,
communications, consumer and industrial applications only. 1.2 Features
„ Low on-state losses „ Low threshold voltage 1.3 Applications
„ Battery management
„ Load Switching „ Battery powered portable equipment
„ Low power DC to DC converters 1.4 Quick reference data
Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C -20 V ID drain current VGS = -4.5 V; Tsp = 25 °C;
see Figure 1 and 3 -4.8 A VGS = -4.5 V; ID = -4.7 A;
VDS = -10 V; Tj = 25 °C;
see Figure 9 and 10 -1.3 -nC VGS = -4.5 V; ID = -2.8 A;
Tj = 25 °C; see Figure 7 and 8 -48 60 mΩ Dynamic characteristics
QGD gate-drain charge Static characteristics
RDSon drain-source on-state
resistance PMN50XP NXP Semiconductors P-channel TrenchMOS extremely low level FET 2. Pinning information
Table 2. Pinning Pin Symbol Description 1 D drain 2 D drain 3 G gate 4 S source 5 D drain 6 D drain Simplified outline Graphic Symbol 6 5 4 1 2 3 D G
S
003aaa671 3. Ordering information
Table 3. Ordering information Type number Package …