Datasheet AD712 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Precision, Low Cost, High Speed, BiFET Dual Op Amp |
| Pages / Page | 21 / 9 — 100. –70. VS = ±15V VCM = 1V p-p. –80. 25°C. 3V rms RL = 2kΩ. –90. CL = … |
| Revision | I |
| File Format / Size | PDF / 408 Kb |
| Document Language | English |
100. –70. VS = ±15V VCM = 1V p-p. –80. 25°C. 3V rms RL = 2kΩ. –90. CL = 100pF. ) 60. R (. –100. HD (. –110. –120. –130. 10k. 100k. FREQUENCY (Hz)
Text Version of Document
AD712
100 –70 VS = ±15V VCM = 1V p-p –80 80 25°C 3V rms RL = 2kΩ –90 CL = 100pF ) 60 B B) d d R ( –100 HD ( CM T 40 –110 20 –120 0 –130
17
10 100 1k 10k 100k 1M
14 0
100 1k 10k 100k
0 3- 3- 82
FREQUENCY (Hz)
82
FREQUENCY (Hz)
00 00 Figure 14. Common-Mode Rejection vs. Frequency Figure 17. Total Harmonic Distortion vs. Frequency
30 1k RL = 2kΩ 25°C ) 25 V ) -p S = ±15V p V √Hz ( V/ 20 (n 100 ING E W G S A E T L 15 AG T VO L E O IS V 10 O 10 UT N P T T U PU O 5 IN 0
5
1
8 1
100k 1M 10M
0
1 10 100 1k 10k 100k
-01 3-
FREQUENCY (Hz)
82
FREQUENCY (Hz)
823 0 00 0 Figure 15. Large Signal Frequency Response Figure 18. Input Noise Voltage Spectral Density
10 25 8 TS 6 OL 20 V 4 ) TO ± s V µ 0 2 V/ 15 1% 0.1% 0.01% OM E ( R 0 T A ERROR 1% 0.1% 0.01% G F R –2 IN 10 EW W S SL –4 T U TP –6 5 OU –8 –10
6
0 0.5 0.6 0.7 0.8 0.9 1.0
01 3-
0 100 200 300 400 500 600 700 800 900
9
SETTLING TIME (µs)
82
INPUT ERROR SIGNAL (mV)
-01 00
(AT SUMMING JUNCTION)
823 00 Figure 16. Output Swing and Error vs. Settling Time Figure 19. Slew Rate vs. Input Error Signal Rev. H | Page 8 of 20 Document Outline FEATURES GENERAL DESCRIPTION CONNECTION DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS SETTLING TIME OPTIMIZING SETTLING TIME OP AMP SETTLING TIME—A MATHEMATICAL MODEL APPLICATIONS INFORMATION GUARDING DAC CONVERTER APPLICATIONS NOISE CHARACTERISTICS DRIVING THE ANALOG INPUT OF AN ADC DRIVING A LARGE CAPACITIVE LOAD FILTERS ACTIVE FILTER APPLICATIONS SECOND-ORDER LOW-PASS FILTER 9-POLE CHEBYCHEV FILTER OUTLINE DIMENSIONS ORDERING GUIDE
100 –70 VS = ±15V VCM = 1V p-p –80 80 25°C 3V rms RL = 2kΩ –90 CL = 100pF ) 60 B B) d d R ( –100 HD ( CM T 40 –110 20 –120 0 –130
17
10 100 1k 10k 100k 1M
14 0
100 1k 10k 100k
0 3- 3- 82
FREQUENCY (Hz)
82
FREQUENCY (Hz)
00 00 Figure 14. Common-Mode Rejection vs. Frequency Figure 17. Total Harmonic Distortion vs. Frequency
30 1k RL = 2kΩ 25°C ) 25 V ) -p S = ±15V p V √Hz ( V/ 20 (n 100 ING E W G S A E T L 15 AG T VO L E O IS V 10 O 10 UT N P T T U PU O 5 IN 0
5
1
8 1
100k 1M 10M
0
1 10 100 1k 10k 100k
-01 3-
FREQUENCY (Hz)
82
FREQUENCY (Hz)
823 0 00 0 Figure 15. Large Signal Frequency Response Figure 18. Input Noise Voltage Spectral Density
10 25 8 TS 6 OL 20 V 4 ) TO ± s V µ 0 2 V/ 15 1% 0.1% 0.01% OM E ( R 0 T A ERROR 1% 0.1% 0.01% G F R –2 IN 10 EW W S SL –4 T U TP –6 5 OU –8 –10
6
0 0.5 0.6 0.7 0.8 0.9 1.0
01 3-
0 100 200 300 400 500 600 700 800 900
9
SETTLING TIME (µs)
82
INPUT ERROR SIGNAL (mV)
-01 00
(AT SUMMING JUNCTION)
823 00 Figure 16. Output Swing and Error vs. Settling Time Figure 19. Slew Rate vs. Input Error Signal Rev. H | Page 8 of 20 Document Outline FEATURES GENERAL DESCRIPTION CONNECTION DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS SETTLING TIME OPTIMIZING SETTLING TIME OP AMP SETTLING TIME—A MATHEMATICAL MODEL APPLICATIONS INFORMATION GUARDING DAC CONVERTER APPLICATIONS NOISE CHARACTERISTICS DRIVING THE ANALOG INPUT OF AN ADC DRIVING A LARGE CAPACITIVE LOAD FILTERS ACTIVE FILTER APPLICATIONS SECOND-ORDER LOW-PASS FILTER 9-POLE CHEBYCHEV FILTER OUTLINE DIMENSIONS ORDERING GUIDE
