Datasheet LT5554 (Analog Devices) - 27
| Manufacturer | Analog Devices |
| Description | Broadband Ultra Low Distortion 7-Bit Digitally Controlled VGA |
| Pages / Page | 32 / 27 — APPLICATIONS INFORMATION. Figure 21. Evaluation Circuit Schematic |
| File Format / Size | PDF / 619 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Figure 21. Evaluation Circuit Schematic
Model Line for this Datasheet
Text Version of Document
LT5554
APPLICATIONS INFORMATION
J5, 40 PINS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SMT-TB V V CC VCC VCC VCC DEC ENB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE V V PG MODE CCO VCCO VCCO VCCO 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VDEC ENB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE VPG MODE VCC VCCO VPG PG1 PG4 R20 R21 R22 R23 R24 R25 R26 10k 10k 10k 10k 10k 10k 10k C11 R28 C14 R31 NOT MOUNTED 47nF 0Ω 47nF 0Ω NOT MOUNTED PG0 PG1 PG2 PG3 PG4 PG5 PG6 J2 J4 C21 C22 C23 C24 C25 C26 C27 PG2 PG3 NOT MOUNTED NOT MOUNTED 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF C12 R29 R30 C13 47nF 0Ω 0Ω 47nF NOT MOUNTED NOT MOUNTED C21 THROUGH C27 ARE NOT MOUNTED R12 R14 NOT MOUNTED NOT MOUNTED VCCO 32 31 30 29 28 27 26 25 C3 C19 0.1μF 4.7μF R8 PG1 GND PG2 PG3 GND PG4 GND GND C4 0Ω 1 24 R5 VDEC GND VCC VCC 68.1Ω 2 23 R3 T2 GND ENB ENABLE 0Ω T1 TC2-1T OUT– IN+ J1 3 22 1:1 DEC GND 2:1 J3 4 21 • • • • IN+ OUT– R7 5 LT5554 20 NC • IN– OUT+ 6 19 IN– DEC GND OUT+ J11 ETC1-1-13 J33 7 18 MACOM GND MODE MODE R4 MINI- R6 8 0Ω CIRCUITS 17 C6 NOT R1 GND V 681Ω CC NOT 47nF MOUNTED 0Ω MOUNTED C5 PG5 GND PG6 PG0 GND STROBE GND GND C8 R2 0.1μF C9 C18 1μF 9 10 11 12 13 14 15 16 0Ω 0.1μF 0.1μF 5554 F21 NOT MOUNTED NOT MOUNTED NOT MOUNTED R17 R16 R33 R27 R34 NOT MOUNTED C16 C17 0Ω 0Ω 0Ω 47nF 47nF NOT MOUNTED J7 NOT MOUNTED NOT MOUNTED PG6 PG0 STROBE J6 R32 C15 0Ω 47nF PG5
Figure 21. Evaluation Circuit Schematic
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APPLICATIONS INFORMATION
J5, 40 PINS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SMT-TB V V CC VCC VCC VCC DEC ENB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE V V PG MODE CCO VCCO VCCO VCCO 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VDEC ENB PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE VPG MODE VCC VCCO VPG PG1 PG4 R20 R21 R22 R23 R24 R25 R26 10k 10k 10k 10k 10k 10k 10k C11 R28 C14 R31 NOT MOUNTED 47nF 0Ω 47nF 0Ω NOT MOUNTED PG0 PG1 PG2 PG3 PG4 PG5 PG6 J2 J4 C21 C22 C23 C24 C25 C26 C27 PG2 PG3 NOT MOUNTED NOT MOUNTED 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF C12 R29 R30 C13 47nF 0Ω 0Ω 47nF NOT MOUNTED NOT MOUNTED C21 THROUGH C27 ARE NOT MOUNTED R12 R14 NOT MOUNTED NOT MOUNTED VCCO 32 31 30 29 28 27 26 25 C3 C19 0.1μF 4.7μF R8 PG1 GND PG2 PG3 GND PG4 GND GND C4 0Ω 1 24 R5 VDEC GND VCC VCC 68.1Ω 2 23 R3 T2 GND ENB ENABLE 0Ω T1 TC2-1T OUT– IN+ J1 3 22 1:1 DEC GND 2:1 J3 4 21 • • • • IN+ OUT– R7 5 LT5554 20 NC • IN– OUT+ 6 19 IN– DEC GND OUT+ J11 ETC1-1-13 J33 7 18 MACOM GND MODE MODE R4 MINI- R6 8 0Ω CIRCUITS 17 C6 NOT R1 GND V 681Ω CC NOT 47nF MOUNTED 0Ω MOUNTED C5 PG5 GND PG6 PG0 GND STROBE GND GND C8 R2 0.1μF C9 C18 1μF 9 10 11 12 13 14 15 16 0Ω 0.1μF 0.1μF 5554 F21 NOT MOUNTED NOT MOUNTED NOT MOUNTED R17 R16 R33 R27 R34 NOT MOUNTED C16 C17 0Ω 0Ω 0Ω 47nF 47nF NOT MOUNTED J7 NOT MOUNTED NOT MOUNTED PG6 PG0 STROBE J6 R32 C15 0Ω 47nF PG5
Figure 21. Evaluation Circuit Schematic
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