Datasheet LT1671 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 60ns, Low Power, Single Supply, Ground-Sensing Comparator |
| Pages / Page | 12 / 3 — ELECTRICAL CHARACTERISTICS. The |
| File Format / Size | PDF / 214 Kb |
| Document Language | English |
ELECTRICAL CHARACTERISTICS. The
Model Line for this Datasheet
Text Version of Document
LT1671
ELECTRICAL CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25
°
C. V+ = 5V, V– = – 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOH Output Voltage Swing High V + ≥ 4.6V, IOUT = 400µA ● 2.7 3.1 V V + ≥ 4.6V, IOUT = 4mA ● 2.4 3.0 V VOL Output Voltage Swing Low IOUT = – 400µA ● 0.3 0.5 V IOUT = – 4mA 0.4 V I+ Positive Supply Current 450 800 µA ● 1000 µA I– Negative Supply Current 75 200 µA ● 250 µA VIH LATCH Pin High Input Voltage ● 2 V VIL LATCH Pin Low Input Voltage ● 0.8 V IIL LATCH Pin Current VLATCH = 0V ● – 1000 – 250 nA tPD1 Propagation Delay ∆VIN = 100mV, VOD = 20mV 60 80 ns ● 110 ns tPD2 Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 85 100 ns ● 130 ns ∆tPD Differential Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 15 30 ns tLPD Latch Propagation Delay (Note 8) 60 ns tSU Latch Setup Time (Note 8) – 15 ns tH Latch Hold Time (Note 8) 35 ns tPW(D) Minimum Disable Pulse Width 30 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
tPD and ∆tPD cannot be measured in automatic handling of a device may be impaired. equipment with low values of overdrive. The LT1671 is 100% tested with a
Note 2:
This parameter is guaranteed to meet specified performance 100mV step and 20mV overdrive. Correlation tests have shown that tPD through design and characterization. It has not been tested. and ∆tPD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct.
Note 3:
The LT1671CS8 and LT1671CMS8 are guaranteed to meet Propagation delay (t specified performance from 0°C to 70°C and are designed, characterized PD) is measured with the overdrive added to the actual V and expected to meet these extended temperature limits, but are not tested OS. Differential propagation delay is defined as: at – 40°C and 85°C. The LT1671IS8 is guaranteed to meet the extended ∆tPD = tPDLH – tPDHL temperature limits.
Note 8:
Latch propagation delay (tLPD) is the delay time for the output to
Note 4:
Input offset voltage (V respond when the LATCH pin is deasserted. Latch setup time (t OS) is defined as the average of the two SU) is the voltages measured by forcing first one output, then the other to 1.4V. interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (t
Note 5:
Input bias current (I H) is the interval after the latch is asserted in B) is defined as the average of the two input which the input signal must remain stable. currents.
Note 6:
Input voltage range is guaranteed in part by CMRR testing and in part by design and characterization. 3
ELECTRICAL CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25
°
C. V+ = 5V, V– = – 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOH Output Voltage Swing High V + ≥ 4.6V, IOUT = 400µA ● 2.7 3.1 V V + ≥ 4.6V, IOUT = 4mA ● 2.4 3.0 V VOL Output Voltage Swing Low IOUT = – 400µA ● 0.3 0.5 V IOUT = – 4mA 0.4 V I+ Positive Supply Current 450 800 µA ● 1000 µA I– Negative Supply Current 75 200 µA ● 250 µA VIH LATCH Pin High Input Voltage ● 2 V VIL LATCH Pin Low Input Voltage ● 0.8 V IIL LATCH Pin Current VLATCH = 0V ● – 1000 – 250 nA tPD1 Propagation Delay ∆VIN = 100mV, VOD = 20mV 60 80 ns ● 110 ns tPD2 Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 85 100 ns ● 130 ns ∆tPD Differential Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV 15 30 ns tLPD Latch Propagation Delay (Note 8) 60 ns tSU Latch Setup Time (Note 8) – 15 ns tH Latch Hold Time (Note 8) 35 ns tPW(D) Minimum Disable Pulse Width 30 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
tPD and ∆tPD cannot be measured in automatic handling of a device may be impaired. equipment with low values of overdrive. The LT1671 is 100% tested with a
Note 2:
This parameter is guaranteed to meet specified performance 100mV step and 20mV overdrive. Correlation tests have shown that tPD through design and characterization. It has not been tested. and ∆tPD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct.
Note 3:
The LT1671CS8 and LT1671CMS8 are guaranteed to meet Propagation delay (t specified performance from 0°C to 70°C and are designed, characterized PD) is measured with the overdrive added to the actual V and expected to meet these extended temperature limits, but are not tested OS. Differential propagation delay is defined as: at – 40°C and 85°C. The LT1671IS8 is guaranteed to meet the extended ∆tPD = tPDLH – tPDHL temperature limits.
Note 8:
Latch propagation delay (tLPD) is the delay time for the output to
Note 4:
Input offset voltage (V respond when the LATCH pin is deasserted. Latch setup time (t OS) is defined as the average of the two SU) is the voltages measured by forcing first one output, then the other to 1.4V. interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (t
Note 5:
Input bias current (I H) is the interval after the latch is asserted in B) is defined as the average of the two input which the input signal must remain stable. currents.
Note 6:
Input voltage range is guaranteed in part by CMRR testing and in part by design and characterization. 3
