Datasheet LT1711, LT1712 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Single/Dual 4.5ns, 3V/5V/±5V, Rail-to-Rail Comparators |
| Pages / Page | 12 / 4 — ELECTRICAL CHARACTERISTICS. The |
| File Format / Size | PDF / 226 Kb |
| Document Language | English |
ELECTRICAL CHARACTERISTICS. The
Model Line for this Datasheet
Text Version of Document
LT1711/LT1712
ELECTRICAL CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. V+ = 5V, V– = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AV Small-Signal Voltage Gain 1 15 V/mV VOH Output Voltage Swing HIGH (Note 8) IOUT = 1mA, VOVERDRIVE = 50mV ● 4.5 4.8 V IOUT = 10mA, VOVERDRIVE = 50mV ● 4.3 4.6 V VOL Output Voltage Swing LOW (Note 8) IOUT = – 1mA, VOVERDRIVE = 50mV ● 0.20 0.4 V IOUT = – 10mA, VOVERDRIVE = 50mV ● 0.30 0.5 V I+ Positive Supply Current (Per Comparator) VOVERDRIVE = 1V 17 22 mA ● 30 mA I– Negative Supply Current (Per Comparator) VOVERDRIVE = 1V 9 12 mA ● 15 mA VIH Latch Pin High Input Voltage ● 2.4 V VIL Latch Pin Low Input Voltage ● 0.8 V IIL Latch Pin Current VLATCH = V+ ● 15 µA tPD Propagation Delay (Notes 6, 11) ∆VIN = 100mV, VOVERDRIVE = 20mV 4.5 6.0 ns ∆VIN = 100mV, VOVERDRIVE = 20mV ● 8.5 ns ∆VIN = 100mV, VOVERDRIVE = 5mV 5.5 ns ∆tPD Differential Propagation Delay (Notes 6, 11) ∆VIN = 100mV, VOVERDRIVE = 20mV 0.5 1.5 ns tr Output Rise Time 10% to 90% 2 ns tf Output Fall Time 90% to 10% 2 ns tLPD Latch Propagation Delay (Note 7) 5 ns tSU Latch Setup Time (Note 7) 1 ns tH Latch Hold Time (Note 7) 0 ns tDPW Minimum Latch Disable Pulse Width (Note 7) 5 ns fMAX Maximum Toggle Frequency VIN = 100mVP-P Sine Wave 100 MHz tJITTER Output Timing Jitter VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz 11 psRMS
Note 1:
Absolute Maximum Ratings are those values beyond which the life interval in which the input signal must remain stable prior to asserting the of a device may be impaired. latch signal. Latch hold time (tH) is the interval after the latch is asserted in
Note 2:
The LT1711C/LT1712C are guaranteed to meet specified which the input signal must remain stable. Latch disable pulse width performance from 0°C to 70°C. They are designed, characterized and (tDPW) is the width of the negative pulse on the latch enable pin that expected to meet specified performance from – 40°C to 85°C but are not latches in new data on the data inputs. tested or QA sampled at these temperatures. The LT1711I/LT1712I are
Note 8:
Output voltage swings are characterized and tested at V+ = 5V and guaranteed to meet specified performance from –40°C to 85°C. V– = 0V. They are guaranteed by design and correlation to meet these
Note 3:
The negative supply should not be greater than the ground pin specifications at V– = – 5V. voltage and the maximum voltage across the positive and negative
Note 9:
The input voltage range is tested under the more demanding supplies should not be greater than 12V. conditions of V+ = 5V and V– = –5V. The LT1711/LT1712 are guaranteed
Note 4:
Input offset voltage (V by design and correlation to meet these specifications at V– = 0V. OS) is measured with the LT1711/LT1712 in a configuration that adds external hysteresis. It is defined as the average of
Note 10:
The LT1711/LT1712 voltage gain is tested at V+ = 5V and the two hysteresis trip points. V– = –5V only. Voltage gain at single supply V+ = 5V and V+ = 2.7V is
Note 5:
Input bias current (I guaranteed by design and correlation. B) is defined as the average of the two input currents.
Note 11:
The LT1711/LT1712 tPD is tested at V+ = 5V and 2.7V with
Note 6:
Propagation delay (t V– = 0V. Propagation delay at V+ = 5V, V– = –5V is guaranteed by design PD) is measured with the overdrive added to the actual V and correlation. OS. Differential propagation delay is defined as: ∆t + – PD = tPD – tPD . Load capacitance is 10pF. Due to test system
Note 12:
Care must be taken to make sure that the LT1711/LT1712 do not requirements, the LT1711/LT1712 propagation delay is specified with a exceed TJMAX when operating with ±5V supplies over the industrial 1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V temperature range. TJMAX is not exceeded for DC inputs, but supply single supplies. current increases with switching frequency (see Typical Performance
Note 7:
Latch propagation delay (t Characteristics). LPD) is the delay time for the output to respond when the latch pin is deasserted. Latch setup time (tSU) is the 4
ELECTRICAL CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. V+ = 5V, V– = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AV Small-Signal Voltage Gain 1 15 V/mV VOH Output Voltage Swing HIGH (Note 8) IOUT = 1mA, VOVERDRIVE = 50mV ● 4.5 4.8 V IOUT = 10mA, VOVERDRIVE = 50mV ● 4.3 4.6 V VOL Output Voltage Swing LOW (Note 8) IOUT = – 1mA, VOVERDRIVE = 50mV ● 0.20 0.4 V IOUT = – 10mA, VOVERDRIVE = 50mV ● 0.30 0.5 V I+ Positive Supply Current (Per Comparator) VOVERDRIVE = 1V 17 22 mA ● 30 mA I– Negative Supply Current (Per Comparator) VOVERDRIVE = 1V 9 12 mA ● 15 mA VIH Latch Pin High Input Voltage ● 2.4 V VIL Latch Pin Low Input Voltage ● 0.8 V IIL Latch Pin Current VLATCH = V+ ● 15 µA tPD Propagation Delay (Notes 6, 11) ∆VIN = 100mV, VOVERDRIVE = 20mV 4.5 6.0 ns ∆VIN = 100mV, VOVERDRIVE = 20mV ● 8.5 ns ∆VIN = 100mV, VOVERDRIVE = 5mV 5.5 ns ∆tPD Differential Propagation Delay (Notes 6, 11) ∆VIN = 100mV, VOVERDRIVE = 20mV 0.5 1.5 ns tr Output Rise Time 10% to 90% 2 ns tf Output Fall Time 90% to 10% 2 ns tLPD Latch Propagation Delay (Note 7) 5 ns tSU Latch Setup Time (Note 7) 1 ns tH Latch Hold Time (Note 7) 0 ns tDPW Minimum Latch Disable Pulse Width (Note 7) 5 ns fMAX Maximum Toggle Frequency VIN = 100mVP-P Sine Wave 100 MHz tJITTER Output Timing Jitter VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz 11 psRMS
Note 1:
Absolute Maximum Ratings are those values beyond which the life interval in which the input signal must remain stable prior to asserting the of a device may be impaired. latch signal. Latch hold time (tH) is the interval after the latch is asserted in
Note 2:
The LT1711C/LT1712C are guaranteed to meet specified which the input signal must remain stable. Latch disable pulse width performance from 0°C to 70°C. They are designed, characterized and (tDPW) is the width of the negative pulse on the latch enable pin that expected to meet specified performance from – 40°C to 85°C but are not latches in new data on the data inputs. tested or QA sampled at these temperatures. The LT1711I/LT1712I are
Note 8:
Output voltage swings are characterized and tested at V+ = 5V and guaranteed to meet specified performance from –40°C to 85°C. V– = 0V. They are guaranteed by design and correlation to meet these
Note 3:
The negative supply should not be greater than the ground pin specifications at V– = – 5V. voltage and the maximum voltage across the positive and negative
Note 9:
The input voltage range is tested under the more demanding supplies should not be greater than 12V. conditions of V+ = 5V and V– = –5V. The LT1711/LT1712 are guaranteed
Note 4:
Input offset voltage (V by design and correlation to meet these specifications at V– = 0V. OS) is measured with the LT1711/LT1712 in a configuration that adds external hysteresis. It is defined as the average of
Note 10:
The LT1711/LT1712 voltage gain is tested at V+ = 5V and the two hysteresis trip points. V– = –5V only. Voltage gain at single supply V+ = 5V and V+ = 2.7V is
Note 5:
Input bias current (I guaranteed by design and correlation. B) is defined as the average of the two input currents.
Note 11:
The LT1711/LT1712 tPD is tested at V+ = 5V and 2.7V with
Note 6:
Propagation delay (t V– = 0V. Propagation delay at V+ = 5V, V– = –5V is guaranteed by design PD) is measured with the overdrive added to the actual V and correlation. OS. Differential propagation delay is defined as: ∆t + – PD = tPD – tPD . Load capacitance is 10pF. Due to test system
Note 12:
Care must be taken to make sure that the LT1711/LT1712 do not requirements, the LT1711/LT1712 propagation delay is specified with a exceed TJMAX when operating with ±5V supplies over the industrial 1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V temperature range. TJMAX is not exceeded for DC inputs, but supply single supplies. current increases with switching frequency (see Typical Performance
Note 7:
Latch propagation delay (t Characteristics). LPD) is the delay time for the output to respond when the latch pin is deasserted. Latch setup time (tSU) is the 4
