Datasheet LT1713, LT1714 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Single/Dual, 7ns, Low Power, 3V/5V/±5V Rail-to-Rail Comparators |
| Pages / Page | 16 / 9 — APPLICATIO S I FOR ATIO. Figure 1. Typical LT1714 Topside Metal for … |
| File Format / Size | PDF / 239 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Figure 1. Typical LT1714 Topside Metal for Multilayer PCB Layout
Model Line for this Datasheet
Text Version of Document
LT1713/LT1714
U U W U APPLICATIO S I FOR ATIO
Poor trace routes and high source impedances are also this isolation as shown in Figure 1, a typical topside layout common sources of problems. Keep trace lengths as of the LT1713/LT1714 on a multilayer PC board. Shown is short as possible and avoid running any output trace the topside metal etch including traces, pin escape vias and adjacent to an input trace to prevent unnecessary cou- the land pads for a GN16 LT1713/LT1714 and its adjacent pling. If output traces are longer than a few inches, X7R 0805 bypass capacitors. The V+, V– and GND traces provide proper termination impedances (typically 100Ω all shield the inputs from the outputs. Although the two V– to 400Ω) to eliminate any reflections that may occur. Also pins are connected internally, they should be shorted to- keep source impedances as low as possible, preferably gether externally as well in order for both to function as much less than 1kΩ. shields. The same is true for the two V+ pins. The two GND The input and output traces should also be isolated from pins are not connected internally, but in most applications one another. Power supply traces can be used to achieve they are both connected directly to the ground plane. 1714 F01
Figure 1. Typical LT1714 Topside Metal for Multilayer PCB Layout
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U U W U APPLICATIO S I FOR ATIO
Poor trace routes and high source impedances are also this isolation as shown in Figure 1, a typical topside layout common sources of problems. Keep trace lengths as of the LT1713/LT1714 on a multilayer PC board. Shown is short as possible and avoid running any output trace the topside metal etch including traces, pin escape vias and adjacent to an input trace to prevent unnecessary cou- the land pads for a GN16 LT1713/LT1714 and its adjacent pling. If output traces are longer than a few inches, X7R 0805 bypass capacitors. The V+, V– and GND traces provide proper termination impedances (typically 100Ω all shield the inputs from the outputs. Although the two V– to 400Ω) to eliminate any reflections that may occur. Also pins are connected internally, they should be shorted to- keep source impedances as low as possible, preferably gether externally as well in order for both to function as much less than 1kΩ. shields. The same is true for the two V+ pins. The two GND The input and output traces should also be isolated from pins are not connected internally, but in most applications one another. Power supply traces can be used to achieve they are both connected directly to the ground plane. 1714 F01
Figure 1. Typical LT1714 Topside Metal for Multilayer PCB Layout
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