Datasheet MCP6141, MCP6142, MCP6143, MCP6144 (Microchip) - 13

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MCP6141/2/3/4 3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE MCP6141 MCP6142 MCP6143 MCP6144
MSOP, MSOP, MSOP, MSOP,
Symbol Description
PDIP, SOT-23-5 PDIP, PDIP, SOT-23-6 PDIP, SOIC SOIC SOIC SOIC 6 1 1 6 1 1 VOUT, VOUTA Analog Output (op amp A) 2 4 2 2 4 2 VIN–, VINA– Inverting Input (op amp A) 3 3 3 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A) 7 5 8 7 6 4 VDD Positive Power Supply — — 5 — — 5 VINB+ Non-inverting Input (op amp B) — — 6 — — 6 VINB– Inverting Input (op amp B) — — 7 — — 7 VOUTB Analog Output (op amp B) — — — — — 8 VOUTC Analog Output (op amp C) — — — — — 9 VINC– Inverting Input (op amp C) — — — — — 10 VINC+ Non-inverting Input (op amp C) 4 2 4 4 2 11 VSS Negative Power Supply — — — — — 12 VIND+ Non-inverting Input (op amp D) — — — — — 13 VIND– Inverting Input (op amp D) — — — — — 14 VOUTD Analog Output (op amp D) — — — 8 5 — CS Chip Select 1, 5, 8 — — 1, 5 — — NC No Internal Connection
3.1 Analog Outputs 3.4 Power Supply Pins
The output pins are low-impedance voltage sources. The positive power supply pin (VDD) is 1.4V to 6.0V higher than the negative power supply pin (VSS). For
3.2 Analog Inputs
normal operation, the other pins are at voltages between VSS and VDD. The non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and V
3.3 CS Digital Input
DD is connected to the supply. VDD will need bypass capacitors. This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation. © 2009 Microchip Technology Inc. DS21668D-page 13 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6141/2/3/4 Family Shows No Phase Reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel to Channel Separation vs. Frequency (MCP6142 and MCP6144 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6143 only). FIGURE 2-33: Input Current vs. Input Voltage (Below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Internal Chip Select (CS) Hysteresis (MCP6143 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 CS Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Stability FIGURE 4-3: Noise Gain for Non-inverting Gain Configuration. FIGURE 4-4: Noise Gain for Inverting Gain Configuration. FIGURE 4-5: Examples of Unstable Circuits for the MCP6141/2/3/4 Family. FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-7: Recommended RISO Values for Capacitive Loads. 4.5 MCP6143 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-8: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-9: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-10: High Side Battery Current Sensor. FIGURE 4-11: Summing Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulation Tool 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information