Datasheet MCP6241, MCP6241R, MCP6241U, MCP62412, MCP62414 (Microchip) - 6
| Manufacturer | Microchip |
| Description | MCP6241/1R/1U/2/4 family of operational amplifier (Op Amp) provides wide bandwidth for the quiescent current |
| Pages / Page | 38 / 6 — MCP6241/1R/1U/2/4. Note:. 10,000. s 20%. ity. 628 Samples. 18%. nc 16% CM … |
| File Format / Size | PDF / 684 Kb |
| Document Language | English |
MCP6241/1R/1U/2/4. Note:. 10,000. s 20%. ity. 628 Samples. 18%. nc 16% CM = VSS. rre. A = -40°C to +125°C. 1,000. u 14%. c c 12%. lta. 10%. of O. 100
Model Line for this Datasheet
Text Version of Document
MCP6241/1R/1U/2/4 Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
10,000 s 20% ity e 628 Samples 18% ns V e nc 16% CM = VSS D rre T e A = -40°C to +125°C 1,000 u 14% g ) c c 12% lta Hz o /
√
10% V V of O e (n 8% is 100 ge o 6% ta N n e 4% rc 2% e Input P 10 0% 2 0 -8 -6 -4 -2 0 2 4 6 8 1.E-0 0.1 1 1.E+ 1 0 1.E+ 10 0 1.E+0 100 1.E+ 1k 0 1.E+ 10k0 1.E+ 100 0 k -1 -1 10 12 0 1 Fre 2 quency (H 3 z) 4 5 Input Offset Voltage Drift (µV/°C) FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
Input Offset Voltage Drift. vs. Frequency.
300 700 ) ) V V V DD = 1.8V V CM = VSS µ 650 200 µ ( e ( e g 600 g 100 lta lta 550 o o 0 t V t V 500 V e T e DD = 5.5V A = -40°C -100 T 450 ffs A = +25°C Offs VDD = 1.8V T O 400 -200 A = +85°C T Input A = +125°C 350 Input -300 300 .4 2 0 2 4 6 8 0 2 4 6 8 0 2 -0 -0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Output Voltage (V) FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
Input Offset Voltage vs. Common Mode Input Voltage at V Output Voltage. DD = 1.8V.
400 35 ) ) A 30 +ISC V VDD = 5.5V 25 300 (µ t (m 20 e n g 15 200 rre 10 lta TA = +125°C o u 5 T 100 A = +85°C t V 0 it C e T T u -5 A = +25°C ffs A = -40°C 0 rc -10 TA = -40°C T O A = +25°C -15 t Ci -20 -100 TA = +85°C -25 hor Input TA = +125°C S -30 -ISC -200 -35 .5 5 0 0 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0 0.0 0. 1.0 1.5 2. 2.5 3. 3.5 4.0 4. 5.0 5.5 6. Common Mode Input Voltage (V) Power Supply Voltage (V) FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Output Short-Circuit Current Common Mode Input Voltage at V vs. Ambient Temperature. DD = 5.5V. DS21882D-page 6 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: PSRR, CMRR vs. Frequency. FIGURE 2-3: Input Bias Current at +85˚C. FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-6: Input Bias Current at +125˚C. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: Input Offset Voltage vs. Output Voltage. FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. FIGURE 2-13: Slew Rate vs. Ambient Temperature. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply (VSS and VDD) 3.4 Exposed Thermal Pad (EP) 4.0 Application infoRmation 4.1 Rail-to-Rail Inputs FIGURE 4-1: The MCP6241/1R/1U/2/4 Show No Phase Reversal. FIGURE 4-2: Simplified Analog Input ESD Structures. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Summing Amplifier Circuit. FIGURE 4-9: Effect of Parasitic Capacitance at the Input. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 Mindi™ Circuit Designer & Simulator 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
10,000 s 20% ity e 628 Samples 18% ns V e nc 16% CM = VSS D rre T e A = -40°C to +125°C 1,000 u 14% g ) c c 12% lta Hz o /
√
10% V V of O e (n 8% is 100 ge o 6% ta N n e 4% rc 2% e Input P 10 0% 2 0 -8 -6 -4 -2 0 2 4 6 8 1.E-0 0.1 1 1.E+ 1 0 1.E+ 10 0 1.E+0 100 1.E+ 1k 0 1.E+ 10k0 1.E+ 100 0 k -1 -1 10 12 0 1 Fre 2 quency (H 3 z) 4 5 Input Offset Voltage Drift (µV/°C) FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
Input Offset Voltage Drift. vs. Frequency.
300 700 ) ) V V V DD = 1.8V V CM = VSS µ 650 200 µ ( e ( e g 600 g 100 lta lta 550 o o 0 t V t V 500 V e T e DD = 5.5V A = -40°C -100 T 450 ffs A = +25°C Offs VDD = 1.8V T O 400 -200 A = +85°C T Input A = +125°C 350 Input -300 300 .4 2 0 2 4 6 8 0 2 4 6 8 0 2 -0 -0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Output Voltage (V) FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
Input Offset Voltage vs. Common Mode Input Voltage at V Output Voltage. DD = 1.8V.
400 35 ) ) A 30 +ISC V VDD = 5.5V 25 300 (µ t (m 20 e n g 15 200 rre 10 lta TA = +125°C o u 5 T 100 A = +85°C t V 0 it C e T T u -5 A = +25°C ffs A = -40°C 0 rc -10 TA = -40°C T O A = +25°C -15 t Ci -20 -100 TA = +85°C -25 hor Input TA = +125°C S -30 -ISC -200 -35 .5 5 0 0 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0 0.0 0. 1.0 1.5 2. 2.5 3. 3.5 4.0 4. 5.0 5.5 6. Common Mode Input Voltage (V) Power Supply Voltage (V) FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Output Short-Circuit Current Common Mode Input Voltage at V vs. Ambient Temperature. DD = 5.5V. DS21882D-page 6 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: PSRR, CMRR vs. Frequency. FIGURE 2-3: Input Bias Current at +85˚C. FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-6: Input Bias Current at +125˚C. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: Input Offset Voltage vs. Output Voltage. FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. FIGURE 2-13: Slew Rate vs. Ambient Temperature. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply (VSS and VDD) 3.4 Exposed Thermal Pad (EP) 4.0 Application infoRmation 4.1 Rail-to-Rail Inputs FIGURE 4-1: The MCP6241/1R/1U/2/4 Show No Phase Reversal. FIGURE 4-2: Simplified Analog Input ESD Structures. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Summing Amplifier Circuit. FIGURE 4-9: Effect of Parasitic Capacitance at the Input. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 Mindi™ Circuit Designer & Simulator 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
