Datasheet MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004 (Microchip) - 14

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MCP6001/1R/1U/2/4 4.3 Capacitive Loads 4.4 Supply Bypass
Driving large capacitive loads can cause stability With this family of operational amplifiers, the power problems for voltage feedback op amps. As the load supply pin (VDD for single-supply) should have a local capacitance increases, the feedback loop’s phase bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm margin decreases and the closed-loop bandwidth is for good high-frequency performance. It also needs a reduced. This produces gain peaking in the frequency bulk capacitor (i.e., 1 µF or larger) within 100 mm to response, with overshoot and ringing in the step provide large, slow currents. This bulk capacitor can be response. While a unity-gain buffer (G = +1) is the most shared with nearby analog parts. sensitive to capacitive loads, all gains show the same general behavior.
4.5 Unused Op Amps
When driving large capacitive loads with these op An unused op amp in a quad package (MCP6004) amps (e.g., > 100 pF when G = +1), a small series should be configured as shown in Figure 4-5. These resistor at the output (RISO in Figure 4-3) improves the circuits prevent the output from toggling and causing feedback loop’s phase margin (stability) by making the crosstalk. Circuits A sets the op amp at its minimum output load resistive at higher frequencies. The noise gain. The resistor divider produces any desired bandwidth will be generally lower than the bandwidth reference voltage within the output voltage range of the with no capacitance load. op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current.
–
RISO
MCP600X
VOUT
¼ MCP6004 (A) ¼ MCP6004 (B)
VIN
+
CL VDD VDD VDD R
FIGURE 4-3:
Output resistor, R 1 ISO stabilizes large capacitive loads. V R REF Figure 4-4 gives recommended R 2 ISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, G R N and the 2 V = V • --------- Signal Gain are equal. For inverting gains, G REF DD N is R + R 1 2 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-5:
Unused Op Amps.
1000
V = 5.0V
)
DD R = 100 k
4.6 PCB Surface Leakage Ω
L
( OIS
In applications where low input bias current is critical,
R d
Printed Circuit Board (PCB) surface leakage effects
e d 100
need to be considered. Surface leakage is caused by
en
G = 1 N G ≥ 2 N humidity, dust or other contamination on the board.
m m
Under low humidity conditions, a typical resistance
eco
between nearby traces is 1012Ω. A 5V difference would
R
cause 5 pA of current to flow; which is greater than the
10
MCP6001/1R/1U/2/4 family’s bias current at 25°C (typ-
10p 100p 1.E-11 1.E-10 1.E-0 1n 9 1.E-0 10n8 Normalized Load Capacitance; CL/GN (F)
ically 1 pA). The easiest way to reduce surface leakage is to use a
FIGURE 4-4:
Recommended RISO values guard ring around sensitive pins (or traces). The guard for Capacitive Loads. ring is biased at the same voltage as the sensitive pin. After selecting R An example of this type of layout is shown in ISO for your circuit, double-check the resulting frequency response peaking and step Figure 4-6. response overshoot. Modify RISO’s value until the response is reasonable. Bench evaluation and simulations with the MCP6001/1R/1U/2/4 SPICE macro model are very helpful. DS21733J-page 14 © 2009 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Bias Current at +85°C. FIGURE 2-8: Input Bias Current at +125°C. FIGURE 2-9: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-10: PSRR, CMRR vs. Frequency. FIGURE 2-11: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Output Voltage Swing vs. Frequency. FIGURE 2-20: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-21: The MCP6001/2/4 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-7: Instrumentation Amplifier with Unity-Gain Buffer Inputs. FIGURE 4-8: Active Second-Order Low-Pass Filter. FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information