Datasheet AD7605-4 (Analog Devices) - 8

Data Sheet AD7605-4 Timing Diagrams t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t4 CS t7 tRESET RESET
002 13503- Figure 2. CONVST x Timing—Reading After a Conversion
t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t6 CS t7 tRESET RESET
003 13503- Figure 3. CONVST x Timing—Reading During a Conversion
CS t9 t8 t t 11 10 RD t16 t13 t t t 14 17 15 DATA: DB15 TO DB0 INVALID V1 V2 V3 V4 t26 t27 t29 t24
004
FRSTDATA
13503- Figure 4. Parallel Mode, Separate CS and RD Pulses
t12 CS AND RD t t 13 16 t17 DATA: V1 V2 V3 V4 DB15 TO DB0
005
FRSTDATA
13503- Figure 5. CS and RD, Linked Parallel Mode Rev. 0 | Page 7 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS ANALOG INPUT Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE TYPICAL CONNECTION DIAGRAM POWER-DOWN MODES CONVERSION CONTROL Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels APPLICATIONS INFORMATION PARALLEL INTERFACE (/SER/BYTE SEL = 0) PARALLEL BYTE (/SER/BYTE SEL = 1, DB15/BYTE SEL = 1) SERIAL INTERFACE (/SER/BYTE SEL = 1) READING DURING CONVERSION LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE