Datasheet OP179, OP279 (Analog Devices) - 6

OP179/OP279 100 60 120 VS
ⴝ
5V VS
ⴝ
5V TA
ⴝ
25
ⴗ
C
冪
Hz TA
ⴝ
25
ⴗ
C
冪
Hz 50 TA
ⴝ
25
ⴗ
C dB 100 VS
ⴞ
2.5V 80 – FREQUENCY
ⴝ
1kHz nV/ nV/ – – 40 80 60 30 60 40 20 40 20 10 20 VOLTAGE NOISE DENSITY VOLTAGE NOISE DENSITY COMMON-MODE REJECTION 0 0 0 1 10 100 1k 10k 0 1 2 3 4 5 100 1k 10k 100k 1M FREQUENCY – Hz COMMON-MODE VOLTAGE – Volts FREQUENCY – Hz
TPC 19. Voltage Noise Density vs. TPC 20. Voltage Noise Density vs. TPC 21. Common-Mode Frequency Common-Mode Voltage Rejection vs. Frequency
THEORY OF OPERATION VPOS
The OP179/OP279 is the latest entry in Analog Devices’ expand- ing family of single-supply devices, designed for the multimedia
R1 R2
and telecom marketplaces. It is a high output current drive,
6k
⍀
3k
⍀ rail-to-rail input /output operational amplifier, powered from a
Q2 Q3
single 5 V supply. It is also intended for other low supply voltage applications where low distortion and high output current drive
Q4
are needed. To combine the attributes of high output current
R3 R4 2.5k
⍀
2.5k
⍀ and low distortion in rail-to-rail input/output operation, novel circuit design techniques are used.
D5 D6 Q1 Q5 Q6 Q9 IN+ IN–
For example, TPC 1 illustrates a simplified equivalent circuit for the OP179/OP279’s input stage. It is comprised of two PNP
D7 D8 D1 D3
differential pairs, Q5-Q6 and Q7-Q8, operating in parallel, with
D2 D4 R5 R6
diode protection networks. Diode networks D5-D6 and D7-D8
4k
⍀
4k Q7
⍀
Q8
serve to clamp the applied differential input voltage to the
I1 I2 – V + O
OP179/OP279, thereby protecting the input transistors against
R7 R8
avalanche damage. The fundamental differences between these
2.2k
⍀
2.2k
⍀
I3
two PNP gain stages are that the Q7-Q8 pair are normally OFF and that their inputs are buffered from the operational amplifier
VNEG
inputs by Q1-D1-D2 and Q9-D3-D4. Operation is best under- stood as a function of the applied common-mode voltage: When Figure 1. OP179/OP279 Equivalent Input Circuit the inputs of the OP179/OP279 are biased midway between the The key issue here is the behavior of the input bias currents supplies, the differential signal path gain is controlled by the in this stage. The input bias currents of the OP179/OP279 over resistively loaded (via R7, R8) Q5-Q6. As the input common-mode the range of common-mode voltages from (VNEG + 1 V) to level is reduced toward the negative supply (VNEG or GND), the (VPOS – 1 V) are the arithmetic sum of the base currents in Q1-Q5 input transistor current sources, I1 and I3, are forced into satura- and Q9-Q6. Outside of this range, the input bias currents are tion, thereby forcing the Q1-D1-D2 and Q9-D3-D4 networks dominated by the base current sum of Q5-Q6 for input signals into cutoff; however, Q5-Q6 remain active, providing input stage close to VNEG, and of Q1-Q5 (Q9-Q6) for input signals close to gain. On the other hand, when the common-mode input voltage VPOS. As a result of this design approach, the input bias currents is increased toward the positive supply, Q5-Q6 are driven into in the OP179/OP279 not only exhibit different amplitudes, but cutoff, Q3 is driven into saturation, and Q4 becomes active, also exhibit different polarities. This input bias current behavior providing bias to the Q7-Q8 differential pair. The point at which is best illustrated in TPC 3. It is, therefore, of paramount the Q7-Q8 differential pair becomes active is approximately equal importance that the effective source impedances connected to to (VPOS – 1 V). the OP179/OP279’s inputs are balanced for optimum dc and ac performance. –6– REV. G