Datasheet AD843 (Analog Devices) - 10

AD843 SAMPLE-AND-HOLD AMPLIFIER CIRCUITS
To make sure the circuit accommodates a wide ± 10 V input range, the gates of the JFETs must be connected to a potential
A Fast Switching Sample & Hold Circuit
A sample-and-hold circuit possessing short acquisition time and near the –15 V supply. The level-shift circuitry (diode D3, PNP low aperture delay can be built using an AD843 and discrete transistor Q7, and NPN transistor Q6) shifts the TTL level S/H JFET switches. The circuit of Figure 25 employs five n-channel command to provide for an adequate pinch-off voltage for the JFETs (with turn-on times of 35 ns) and an AD843 op amp JFET switches over the full input voltage range. (which can settle to 0.01% in 135 ns). The circuit has an aper- The JFETs Q2, Q3, Q4 and Q5 across the two hold capacitors ture delay time of 50 ns and an acquisition time of 1 µs or less. ensure signal acquisition for all conditions of VIN and VOUT This circuit is based on a noninverting open loop architecture, when the circuit switches from the sample to the hold mode. using a differential hold capacitor to reduce the effects of pedes- Transistor Q1 provides an extra stage of isolation between the tal error. The charge that is removed from CH1 by Q2 and Q3 output of amplifier A1 and the hold capacitor CH1. is offset by the charge removed from CH2 by Q4 and Q5. This When selecting capacitors for use in a sample-and-hold circuit, circuit can tolerate low hold capacitor values (approximately the designer should choose those types with low dielectric 100 pF), which improve acquisition time, due to the small gate- absorption and low temperature coefficients. Silvered-mica to-drain capacitance of the discrete JFETs. Although pedestal capacitors exhibit low (0 to 100 ppm/°C) temperature coeffi- error will vary with input signal level, making trimming more cients and will still work in temperatures exceeding 200°C. It is difficult, the circuit has the advantages of high bandwidth and also recommend that the user test the chosen capacitor to insure short acquisition times. In addition, it will exhibit some that its value closely matches that printed on it since not all nonlinearity because both amplifiers are operating with a com- capacitors are fully tested by their manufacturers for absolute mon-mode input. Amplifier A2, however, contributes less than tolerance. 0.025% linearity error, due to its 72 dB common-mode rejec- tion ratio. Figure 25. A Fast Switching Sample-and-Hold Amplifier
A PING-PONG S/H AMPLIFIER
A high speed CB amplifier, A1, follows the input signal. U1, a For improved throughput over the circuit of Figure 25, a “ping- dual wideband “T” switch, connects the input buffer amp to pong” architecture may be used. A ping-pong circuit overcomes one of the two output amplifiers while selecting the complemen- some of the problems associated with high speed S/H amplifiers tary amplifier to drive the A/D input. For example, when by allowing the use of a larger hold capacitor for a given sample “select” is at logic high, A1 drives CH1, A2 tracks the input sig- rate: this will reduce the associated feedthrough, droop and ped- nal and the output of A3 is connected to the input of the A/D estal errors. converter. At the same time, A3 holds an analog value and its output is connected to the input of the A/D converter. When the Figure 26 illustrates a simple, four-chip ping-pong sample-and- select command goes to logic LOW, the two output amplifiers hold amplifier circuit. This design increases throughput by using alternate functions. one channel to acquire a new sample while another channel holds the previous sample. Instead of having to reacquire the Since the input to the A/D converter is the alternated “held” signal when switching from hold to sample mode, it alternately outputs from A1 and A2, the offset voltage mismatch of the two connects the outputs from Channel 1 or from Channel 2 to the amplifiers will show up as nonlinearity and, therefore, distortion A/D converter. In this case, the throughput is the slew rate and in the output signal. To minimize this, potentiometers can be settling time of the output amplifiers, A2 and A3. used to adjust the offsets of the output amplifiers until they are REV. D –9–