Datasheet OP37 (Analog Devices) - 6

OP37 BINDING DIAGRAM 1. NULL 2. (–) INPUT 1 3. (+) INPUT 4. V– 1990 6. OUTPUT 1427U 7. V+ 8 8. NULL 2 3 7 4 6 (V Wafer Test Limits S = 15 V, TA = 25 C for OP37N, OP37G, and OP37GR devices; TA = 125 C for OP37NT and OP37GT devices, unless otherwise noted.) OP37NT OP37N OP37GT OP37G OP37GR Parameter Symbol Conditions Limit Limit Limit Limit Limit Unit
Input Offset Voltage VOS Note 1 60 35 200 60 100 mV MAX Input Offset Current IOS 50 35 85 50 75 nA MAX Input Bias Current I ± B 60 ±40 ±95 ±55 ±80 nA MAX Input Voltage Range IVR ±10.3 ±11 ±10.3 ±11 ±11 V MIN Common Mode Rejection Ratio CMRR VCM = ± 11 V 108 114 100 106 100 dB MIN Power Supply Rejection Ratio PSRR TA = 25∞C, VS = ±4 V to ±18 V 10 10 10 10 20 mV/V MAX TA = 125∞C, VS = ±4.5 V to ±18 V 16 20 mV/V MAX Large-Signal Voltage Gain AVO RL ≥ 2 kW, VO = ±10 V 600 1000 500 1000 700 V/mV MIN RL ≥ 1 kW, VO = ±10 V 800 800 V/mV MIN Output Voltage Swing VO RL ≥ 2 kW ±11.5 ±12 ±11 ±12 ±11.5 V MIN RL ≥ 600 kW ±10 ±10 ±10 V MIN Power Consumption Pd VO = 0 140 140 170 mW MAX NOTES For 25∞C characterlstics of OP37NT and OP37GT devices, see OP37N and OP37G characteristics, respectively. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. REV. B –5– Document Outline FEATURES GENERAL DESCRIPTION PIN CONNECTIONS SIMPLIFIED SCHEMATIC ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE SPECIFICATIONS BINDING DIAGRAM Wafer Test Limits Typical Electrical Characteristics Typical Performance Characteristics APPLICATIONS INFORMATION Offset Voltage Adjustment Noise Measurements Optimizing Linearity Instrumentation Amplifier Comments on Noise Audio Applications OUTLINE DIMENSIONS Revision History