Datasheet LTC1043 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Dual Precision Instrumentation Switched-Capacitor Building Block |
| Pages / Page | 16 / 6 — APPLICATIO S I FOR ATIO. Shielding the Sampling Capacitor for Very High … |
| File Format / Size | PDF / 241 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Shielding the Sampling Capacitor for Very High CMRR. Switch Charge Injection
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LTC1043
U U W U APPLICATIO S I FOR ATIO
shorting Pins 7 and 13 and by observing, with a precision
Shielding the Sampling Capacitor for Very High CMRR
DVM, the change of the voltage across CH with respect to Internal or external parasitic capacitors from the C+ pin(s) an input CM voltage variation. During the sampling and to ground affect the CMRR of the LTC1043 (Figure 1). holding mode, charges are being transferred and minute The common mode error due to the internal junction voltage transients will appear across the holding capaci- capacitances of the C+ Pin(s) 2 and 11 is cancelled through tor. Although the RON on the switches is low enough to internal circuitry. The C+ pin, therefore, should be used as allow fast settling, as the sampling frequency increases, the top plate of the sampling capacitor. The interpin the rate of charge transfer increases and the average capacitance between pin 2 and dummy Pin 1 (11 and 10) voltage measured with a DVM across it will increase appears in parallel with the sampling capacitor so it does proportionally; this causes the CMRR of the sampled data not degrade the CMRR. A shield placed underneath system, as seen by a “continuous” instrument (DVM), to the sampling capacitor and connected to either Pin 1 or 3 decrease (Figure 2). helps to boost the CMRR in excess of 120dB (Figure 5).
Switch Charge Injection
Excessive external parasitic capacitance between the C– pins and ground indirectly degrades CMRR; this becomes Figure 3 shows one out of the eight switches of the visible especially when the LTC1043 is used with clock LTC1043, configured as a basic sample-and-hold circuit. frequencies above 2kHz. Because of this, if a shield is When the switch opens, a ‘‘hold step’’ is observed and its used, the parasitic capacitance between the shield and magnitude depends on the value of the input voltage. circuit ground should be minimized. Figure 4 shows charge injected into the hold capacitor. For instance, a 2pCb of charge injected into a 0.01µF capacitor It is recommended that the outer plate of the sampling causes a 200µV hold step. As shown in Figure 4, there is capacitor be connected to the C– pin(s). a predictable and repeatable charge injection cancellation when the input voltage is close to half the supply voltage
Input Pins, SCR Sensitivity
of the LTC1043. This is a unique feature of this product, An internal 60Ω resistor is connected in series with the containing charge-balanced switches fabricated with a input of the switches (Pins 5, 6, 7, 8, 13, 14, 15, 18) and self-aligning gate CMOS process. Any switch of the it is included in the RON specification. When the input LTC1043, when powered with symmetrical dual supplies, voltage exceeds the power supply by a diode drop, current will sample-and-hold small signals around ground with- will flow into the input pin(s). The LTC1043 will not latch out any significant error. until the input current reaches 2mA–3mA. The device will 140 CS = CH = 1µF 5V 120 CS = 1µF, CZH = 0.1µF 2 6 + 100 1/2 LTC1013 V 1/8 LTC1043 OUT – 80 VIN 1000pF CMRR (dB) –5V 60 V+ SAMPLE 40 HOLD TO PIN 16 0V LTC1043 • AI03 20 100 1k 10k 100k fOSC (Hz) LTC1043 • AI02
Figure 2. CMRR vs Sampling Frequency Figure 3
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U U W U APPLICATIO S I FOR ATIO
shorting Pins 7 and 13 and by observing, with a precision
Shielding the Sampling Capacitor for Very High CMRR
DVM, the change of the voltage across CH with respect to Internal or external parasitic capacitors from the C+ pin(s) an input CM voltage variation. During the sampling and to ground affect the CMRR of the LTC1043 (Figure 1). holding mode, charges are being transferred and minute The common mode error due to the internal junction voltage transients will appear across the holding capaci- capacitances of the C+ Pin(s) 2 and 11 is cancelled through tor. Although the RON on the switches is low enough to internal circuitry. The C+ pin, therefore, should be used as allow fast settling, as the sampling frequency increases, the top plate of the sampling capacitor. The interpin the rate of charge transfer increases and the average capacitance between pin 2 and dummy Pin 1 (11 and 10) voltage measured with a DVM across it will increase appears in parallel with the sampling capacitor so it does proportionally; this causes the CMRR of the sampled data not degrade the CMRR. A shield placed underneath system, as seen by a “continuous” instrument (DVM), to the sampling capacitor and connected to either Pin 1 or 3 decrease (Figure 2). helps to boost the CMRR in excess of 120dB (Figure 5).
Switch Charge Injection
Excessive external parasitic capacitance between the C– pins and ground indirectly degrades CMRR; this becomes Figure 3 shows one out of the eight switches of the visible especially when the LTC1043 is used with clock LTC1043, configured as a basic sample-and-hold circuit. frequencies above 2kHz. Because of this, if a shield is When the switch opens, a ‘‘hold step’’ is observed and its used, the parasitic capacitance between the shield and magnitude depends on the value of the input voltage. circuit ground should be minimized. Figure 4 shows charge injected into the hold capacitor. For instance, a 2pCb of charge injected into a 0.01µF capacitor It is recommended that the outer plate of the sampling causes a 200µV hold step. As shown in Figure 4, there is capacitor be connected to the C– pin(s). a predictable and repeatable charge injection cancellation when the input voltage is close to half the supply voltage
Input Pins, SCR Sensitivity
of the LTC1043. This is a unique feature of this product, An internal 60Ω resistor is connected in series with the containing charge-balanced switches fabricated with a input of the switches (Pins 5, 6, 7, 8, 13, 14, 15, 18) and self-aligning gate CMOS process. Any switch of the it is included in the RON specification. When the input LTC1043, when powered with symmetrical dual supplies, voltage exceeds the power supply by a diode drop, current will sample-and-hold small signals around ground with- will flow into the input pin(s). The LTC1043 will not latch out any significant error. until the input current reaches 2mA–3mA. The device will 140 CS = CH = 1µF 5V 120 CS = 1µF, CZH = 0.1µF 2 6 + 100 1/2 LTC1013 V 1/8 LTC1043 OUT – 80 VIN 1000pF CMRR (dB) –5V 60 V+ SAMPLE 40 HOLD TO PIN 16 0V LTC1043 • AI03 20 100 1k 10k 100k fOSC (Hz) LTC1043 • AI02
Figure 2. CMRR vs Sampling Frequency Figure 3
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