Datasheet LTC1091, LTC1092, LTC1093, LTC1094 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 1-, 2-, 6- and 8-Channel, 10-Bit Serial I/O Data Acquisition Systems |
| Pages / Page | 32 / 9 — PI FU CTIO S. VREF (Pin 11)(LTC1093):. CLK (Pin 15/Pin 18):. REF +, REF – … |
| File Format / Size | PDF / 288 Kb |
| Document Language | English |
PI FU CTIO S. VREF (Pin 11)(LTC1093):. CLK (Pin 15/Pin 18):. REF +, REF – (Pins 13, 14 )(LTC1094):. VCC (Pin 16)(LTC1093):
Model Line for this Datasheet
Text Version of Document
LTC1091/LTC1092 LTC1093/LTC1094
U U U PI FU CTIO S VREF (Pin 11)(LTC1093):
Reference Input. The reference
CLK (Pin 15/Pin 18):
Shift Clock. This clock synchronizes input must be kept free of noise with respect to AGND. the serial data transfer.
REF +, REF – (Pins 13, 14 )(LTC1094):
Reference Input.
VCC (Pin 16)(LTC1093):
Positive Supply. This supply The reference input must be kept free of noise with respect must be kept free of noise and ripple by bypassing directly to AGND. to the analog ground plane.
DIN (Pin 12/Pin 15):
Data Input. The A/D configuration
AVCC, DVCC (Pins 19, 20)(LTC1094):
Positive Supply. word is shifted into this input. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. AV
D
CC and
OUT (Pin 13/Pin 16):
Digital Data Output. The A/D con- DV version result is shifted out of this output. CC should be tied together on the LTC1094.
CS (Pin 14/Pin 17):
Chip Select Input. A logic low on this input enables the LTC1093/LTC1094.
W BLOCK DIAGRA (Pin numbers refer to LTC1094)
DVCC 19 18 CLK AVCC 20 INPUT D 15 SHIFT OUTPUT IN REGISTER SHIFT 16 DOUT REGISTER CH0 1 SAMPLE- CH1 2 AND-HOLD COMP CH2 3 CH3 4 10-BIT ANALOG CH4 5 SAR INPUT MUX CH5 6 10-BIT CAPACITIVE CH6 7 DAC CH7 8 COM 9 CONTROL AND 17 CS 10 11 12 13 14 TIMING V– REF– REF+ DGND AGND 1091/2/3/4 BD 9
U U U PI FU CTIO S VREF (Pin 11)(LTC1093):
Reference Input. The reference
CLK (Pin 15/Pin 18):
Shift Clock. This clock synchronizes input must be kept free of noise with respect to AGND. the serial data transfer.
REF +, REF – (Pins 13, 14 )(LTC1094):
Reference Input.
VCC (Pin 16)(LTC1093):
Positive Supply. This supply The reference input must be kept free of noise with respect must be kept free of noise and ripple by bypassing directly to AGND. to the analog ground plane.
DIN (Pin 12/Pin 15):
Data Input. The A/D configuration
AVCC, DVCC (Pins 19, 20)(LTC1094):
Positive Supply. word is shifted into this input. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. AV
D
CC and
OUT (Pin 13/Pin 16):
Digital Data Output. The A/D con- DV version result is shifted out of this output. CC should be tied together on the LTC1094.
CS (Pin 14/Pin 17):
Chip Select Input. A logic low on this input enables the LTC1093/LTC1094.
W BLOCK DIAGRA (Pin numbers refer to LTC1094)
DVCC 19 18 CLK AVCC 20 INPUT D 15 SHIFT OUTPUT IN REGISTER SHIFT 16 DOUT REGISTER CH0 1 SAMPLE- CH1 2 AND-HOLD COMP CH2 3 CH3 4 10-BIT ANALOG CH4 5 SAR INPUT MUX CH5 6 10-BIT CAPACITIVE CH6 7 DAC CH7 8 COM 9 CONTROL AND 17 CS 10 11 12 13 14 TIMING V– REF– REF+ DGND AGND 1091/2/3/4 BD 9
