Datasheet LTC1272 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 12-Bit, 3µs, 250kHz Sampling A/D Converter |
| Pages / Page | 22 / 6 — PIN FUNCTIONS. AIN (Pin 1):. HBEN (Pin 19):. REF (Pin 2):. AGND (Pin 3):. … |
| File Format / Size | PDF / 297 Kb |
| Document Language | English |
PIN FUNCTIONS. AIN (Pin 1):. HBEN (Pin 19):. REF (Pin 2):. AGND (Pin 3):. RD (Pin 20):. D11 to D4 (Pins 4-11):. DGND (Pin 12):
Model Line for this Datasheet
- LTC1272-3ACN#PBF LTC1272-3ACSW#PBF LTC1272-3ACSW#TRPBF LTC1272-3CCN#PBF LTC1272-3CCSW#PBF LTC1272-3CCSW#TRPBF LTC1272-8ACN#PBF LTC1272-8ACSW#PBF LTC1272-8ACSW#TRPBF LTC1272-8CCN#PBF LTC1272-8CCSW#PBF LTC1272-8CCSW#TRPBF
Text Version of Document
LTC1272
PIN FUNCTIONS AIN (Pin 1):
Analog Input, 0V to 5V Unipolar Input.
HBEN (Pin 19):
High Byte Enable Input. This pin is used
V
to multiplex the internal 12-bit conversion result into the
REF (Pin 2):
2.42V Reference Output. When plugging into an AD7572 socket, reverse the reference bypass capacitor lower bit outputs (D7 to D0/8). See table below. HBEN polarity and short the 10Ω series resistor. also disables conversion starts when HIGH.
AGND (Pin 3):
Analog Ground.
RD (Pin 20):
Read Input. This active low signal starts a conversion when CS and HBEN are low. RD also enables
D11 to D4 (Pins 4-11):
Three-State Data Outputs. the output drivers when CS is low.
DGND (Pin 12):
Digital Ground.
CS (Pin 21):
The Chip Select Input must be low for the
D3/11 to D0/8 (Pins 13-16):
Three-State Data Outputs. ADC to recognize RD and HBEN inputs.
CLK IN (Pin 17):
Clock Input. An external TTL/CMOS
BUSY (Pin 22):
The BUSY Output is low when a conver- compatible clock may be applied to this pin or a crystal sion is in progress. can be connected between CLK IN and CLK OUT.
NC (Pin 23):
Not Connected Internally. The LTC1272 does
CLK OUT (Pin 18):
Clock Output. An inverted CLK IN signal not require negative supply. This pin can accommodate appears at this pin. the –15V required by the AD7572 without problems.
VDD (Pin 24):
Positive Supply, 5V.
Data Bus Output, CS and RD = LOW Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8 * D11...D0/8 are the ADC data output pins. DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity
1.0 VDD = 5V fCLK = 4MHz 0.5 0 INL ERROR (LSBs) –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1272 • G01 1272fc 6 For more information www.linear.com/1272 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS INTERNAL REFERENCE CHARACTERISTICS DIGITAL AND DC ELECTRICAL CHARACTERISTICS DYNAMIC ACCURACY ANALOG INPUT TIMING CHARACTERISTICS PIN FUNCTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION REVISION HISTORY PACKAGE DESCRIPTION
PIN FUNCTIONS AIN (Pin 1):
Analog Input, 0V to 5V Unipolar Input.
HBEN (Pin 19):
High Byte Enable Input. This pin is used
V
to multiplex the internal 12-bit conversion result into the
REF (Pin 2):
2.42V Reference Output. When plugging into an AD7572 socket, reverse the reference bypass capacitor lower bit outputs (D7 to D0/8). See table below. HBEN polarity and short the 10Ω series resistor. also disables conversion starts when HIGH.
AGND (Pin 3):
Analog Ground.
RD (Pin 20):
Read Input. This active low signal starts a conversion when CS and HBEN are low. RD also enables
D11 to D4 (Pins 4-11):
Three-State Data Outputs. the output drivers when CS is low.
DGND (Pin 12):
Digital Ground.
CS (Pin 21):
The Chip Select Input must be low for the
D3/11 to D0/8 (Pins 13-16):
Three-State Data Outputs. ADC to recognize RD and HBEN inputs.
CLK IN (Pin 17):
Clock Input. An external TTL/CMOS
BUSY (Pin 22):
The BUSY Output is low when a conver- compatible clock may be applied to this pin or a crystal sion is in progress. can be connected between CLK IN and CLK OUT.
NC (Pin 23):
Not Connected Internally. The LTC1272 does
CLK OUT (Pin 18):
Clock Output. An inverted CLK IN signal not require negative supply. This pin can accommodate appears at this pin. the –15V required by the AD7572 without problems.
VDD (Pin 24):
Positive Supply, 5V.
Data Bus Output, CS and RD = LOW Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8 * D11...D0/8 are the ADC data output pins. DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity
1.0 VDD = 5V fCLK = 4MHz 0.5 0 INL ERROR (LSBs) –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1272 • G01 1272fc 6 For more information www.linear.com/1272 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS INTERNAL REFERENCE CHARACTERISTICS DIGITAL AND DC ELECTRICAL CHARACTERISTICS DYNAMIC ACCURACY ANALOG INPUT TIMING CHARACTERISTICS PIN FUNCTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION REVISION HISTORY PACKAGE DESCRIPTION
