Datasheet LTC1279 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 12-Bit, 600ksps Sampling A/D Converter with Shutdown |
| Pages / Page | 16 / 7 — PI FU CTIO S. AIN (Pin 1):. VREF (Pin 2):. RD (Pin 20):. AGND (Pin 3):. … |
| File Format / Size | PDF / 286 Kb |
| Document Language | English |
PI FU CTIO S. AIN (Pin 1):. VREF (Pin 2):. RD (Pin 20):. AGND (Pin 3):. CS (Pin 21):. D11 to D4 (Pins 11 to 4):. DGND (Pin 12):
Model Line for this Datasheet
Text Version of Document
LTC1279
U U U PI FU CTIO S AIN (Pin 1):
Analog Input. 0V to 5V (Unipolar), ±2.5V conversion. The LTC1279 responds to CONVST signal (Bipolar). only if the signal applied to CS is a logic low.
VREF (Pin 2):
2.42V Reference Output. Bypass to AGND
RD (Pin 20):
READ Input. A logic low signal applied to (10µF tantalum in parallel with 0.1µF ceramic). this pin enables the output data drivers when the signal applied to the CS pin is a logic low.
AGND (Pin 3):
Analog Ground.
CS (Pin 21):
The CHIP SELECT input must be a logic low
D11 to D4 (Pins 11 to 4):
Three-State Data Outputs. for the ADC to recognize the signals applied to the D11 is the Most Significant Bit. CONVST and RD inputs.
DGND (Pin 12):
Digital Ground.
BUSY (Pin 22):
The BUSY output shows the converter
D3 to D0 (Pins 13 to 16):
Three-State Data Outputs. status. It is a logic low during a conversion.
DVDD (Pin 17 ):
Digital Power Supply, 5V. Tie to AVDD pin.
VSS (Pin 23):
Negative Supply. – 5V will select bipolar
SHDN (Pin 18):
Power Shutdown. The LTC1279 pow- operation. Bypass to AGND with 0.1µF ceramic. Tie to ers down when SHDN is low. analog ground to select unipolar operation.
CONVST (Pin 19):
Conversion Start Input. It is active
AVDD (Pin 24):
Positive Supply, 5V. Bypass to AGND low. The falling edge of the CONVST signal initiates a (10µF tantalum in parallel with 0.1µF ceramic).
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE A AV IN DD ZEROING SWITCH DVDD 2.42V REF VSS (0V FOR UNIPOLAR MODE V OR –5V FOR BIPOLAR MODE) REF COMPAR- 12-BIT CAPACITIVE DAC ATOR 12 AGND 12 D11 SUCCESSIVE APPROXIMATION • OUTPUT LATCHES • REGISTER • DGND D0 1279 BD INTERNAL CONTROL LOGIC CLOCK SHDN CONVST RD CS BUSY 7
U U U PI FU CTIO S AIN (Pin 1):
Analog Input. 0V to 5V (Unipolar), ±2.5V conversion. The LTC1279 responds to CONVST signal (Bipolar). only if the signal applied to CS is a logic low.
VREF (Pin 2):
2.42V Reference Output. Bypass to AGND
RD (Pin 20):
READ Input. A logic low signal applied to (10µF tantalum in parallel with 0.1µF ceramic). this pin enables the output data drivers when the signal applied to the CS pin is a logic low.
AGND (Pin 3):
Analog Ground.
CS (Pin 21):
The CHIP SELECT input must be a logic low
D11 to D4 (Pins 11 to 4):
Three-State Data Outputs. for the ADC to recognize the signals applied to the D11 is the Most Significant Bit. CONVST and RD inputs.
DGND (Pin 12):
Digital Ground.
BUSY (Pin 22):
The BUSY output shows the converter
D3 to D0 (Pins 13 to 16):
Three-State Data Outputs. status. It is a logic low during a conversion.
DVDD (Pin 17 ):
Digital Power Supply, 5V. Tie to AVDD pin.
VSS (Pin 23):
Negative Supply. – 5V will select bipolar
SHDN (Pin 18):
Power Shutdown. The LTC1279 pow- operation. Bypass to AGND with 0.1µF ceramic. Tie to ers down when SHDN is low. analog ground to select unipolar operation.
CONVST (Pin 19):
Conversion Start Input. It is active
AVDD (Pin 24):
Positive Supply, 5V. Bypass to AGND low. The falling edge of the CONVST signal initiates a (10µF tantalum in parallel with 0.1µF ceramic).
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE A AV IN DD ZEROING SWITCH DVDD 2.42V REF VSS (0V FOR UNIPOLAR MODE V OR –5V FOR BIPOLAR MODE) REF COMPAR- 12-BIT CAPACITIVE DAC ATOR 12 AGND 12 D11 SUCCESSIVE APPROXIMATION • OUTPUT LATCHES • REGISTER • DGND D0 1279 BD INTERNAL CONTROL LOGIC CLOCK SHDN CONVST RD CS BUSY 7
