Datasheet LTC1290 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Single Chip 12-Bit Data Acquisition System |
| Pages / Page | 32 / 8 — PI FU CTIO S. DIN (Pin 17):. ACLK (Pin 19):. SCLK (Pin 18):. VCC (Pin … |
| File Format / Size | PDF / 633 Kb |
| Document Language | English |
PI FU CTIO S. DIN (Pin 17):. ACLK (Pin 19):. SCLK (Pin 18):. VCC (Pin 20):. BLOCK DIAGRAM. TEST CIRCUITS
Model Line for this Datasheet
- LTC1290BCN#PBF LTC1290BCN#PBF LTC1290BCSW#PBF LTC1290BCSW#PBF LTC1290BCSW#TRPBF LTC1290BCSW#TRPBF LTC1290BIN#PBF LTC1290BIN#PBF LTC1290BISW#PBF LTC1290BISW#PBF LTC1290BISW#TRPBF LTC1290BISW#TRPBF LTC1290CCN#PBF LTC1290CCN#PBF LTC1290CCSW#PBF LTC1290CCSW#PBF LTC1290CCSW#TRPBF LTC1290CCSW#TRPBF LTC1290CIN#PBF LTC1290CIN#PBF LTC1290CISW#PBF LTC1290CISW#PBF LTC1290CISW#TRPBF LTC1290CISW#TRPBF LTC1290DCN#PBF LTC1290DCN#PBF LTC1290DCSW#PBF LTC1290DCSW#PBF LTC1290DCSW#TRPBF LTC1290DCSW#TRPBF LTC1290DIN#PBF LTC1290DIN#PBF LTC1290DISW#PBF LTC1290DISW#PBF LTC1290DISW#TRPBF LTC1290DISW#TRPBF
Text Version of Document
LTC1290
U U U PI FU CTIO S DIN (Pin 17):
Digital Data Input. The A/D configuration
ACLK (Pin 19):
A/D Conversion Clock. This clock controls word is shifted into this input after CS is recognized. the A/D conversion process.
SCLK (Pin 18):
Shift Clock. This clock synchronizes the
VCC (Pin 20):
Positive Supply. This supply must be kept serial data transfer. free of noise and ripple by bypassing directly to the analog ground plane.
BLOCK DIAGRAM
18 20 SCLK VCC INPUT 17 OUTPUT 16 D SHIFT SHIFT D IN OUT REGISTER REGISTER 1 CH0 SAMPLE- 2 CH1 AND- 3 HOLD CH2 COMP 4 CH3 ANALOG 5 12-BIT INPUT MUX CH4 SAR 6 CH5 12-BIT 7 CH6 CAPACITIVE 8 DAC CH7 9 COM 19 ACLK CONTROL 15 10 11 12 13 14 AND CS TIMING DGND AGND V– REF– REF+ LTC1290 • BD
TEST CIRCUITS On and Off Channel Leakage Current Load Circuit for tdis and ten
5V ION TEST POINT A ON CHANNEL I 5V WAVEFORM 2 OFF 3k DOUT A WAVEFORM 1 • 100pF OFF • CHANNELS • LTC1290 • TC02 • POLARITY LTC1290 • TC01 1290fe 8
U U U PI FU CTIO S DIN (Pin 17):
Digital Data Input. The A/D configuration
ACLK (Pin 19):
A/D Conversion Clock. This clock controls word is shifted into this input after CS is recognized. the A/D conversion process.
SCLK (Pin 18):
Shift Clock. This clock synchronizes the
VCC (Pin 20):
Positive Supply. This supply must be kept serial data transfer. free of noise and ripple by bypassing directly to the analog ground plane.
BLOCK DIAGRAM
18 20 SCLK VCC INPUT 17 OUTPUT 16 D SHIFT SHIFT D IN OUT REGISTER REGISTER 1 CH0 SAMPLE- 2 CH1 AND- 3 HOLD CH2 COMP 4 CH3 ANALOG 5 12-BIT INPUT MUX CH4 SAR 6 CH5 12-BIT 7 CH6 CAPACITIVE 8 DAC CH7 9 COM 19 ACLK CONTROL 15 10 11 12 13 14 AND CS TIMING DGND AGND V– REF– REF+ LTC1290 • BD
TEST CIRCUITS On and Off Channel Leakage Current Load Circuit for tdis and ten
5V ION TEST POINT A ON CHANNEL I 5V WAVEFORM 2 OFF 3k DOUT A WAVEFORM 1 • 100pF OFF • CHANNELS • LTC1290 • TC02 • POLARITY LTC1290 • TC01 1290fe 8
