Datasheet LTC1409 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 12-Bit, 800ksps Sampling A/D Converter with Shutdown |
| Pages / Page | 20 / 4 — W U. POWER REQUIRE E TS (Note 5). SYMBOL. PARAMETER. CONDITIONS. MIN. … |
| File Format / Size | PDF / 356 Kb |
| Document Language | English |
W U. POWER REQUIRE E TS (Note 5). SYMBOL. PARAMETER. CONDITIONS. MIN. TYP. MAX. UNITS. TI I G CHARACTERISTICS (Note 5). Note 5:. Note 1:
Model Line for this Datasheet
Text Version of Document
LTC1409
W U POWER REQUIRE E TS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ISS Negative Supply Current CS High ● 10 15 mA Nap Mode CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V 10 µA Sleep Mode CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V 1 µA PDISS Power Dissipation ● 80 120 mW Nap Mode CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V 3.8 6 mW Sleep Mode CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V 0.01 mW
W U TI I G CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency ● 800 kHz tCONV Conversion Time ● 900 1250 ns tACQ Acquisition Time ● 150 ns t1 CS to RD Setup Time (Notes 9, 10) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 10 ns t3 NAP/SLP↓ to SHDN↓ Setup Time (Notes 9, 10) ● 10 ns t4 SHDN↑ to CONVST↓ Wake-Up Time (Note 10) 200 ns t5 CONVST Low Time (Notes 10, 11) ● 50 ns t6 CONVST to BUSY Delay CL = 25pF 10 ns ● 60 ns t7 Data Ready Before BUSY↑ 20 35 ns ● 15 ns t8 Delay Between Conversions (Note 10) ● 40 ns t9 Wait Time RD↓ After BUSY↑ ● – 5 ns t10 Data Access Time After RD↓ CL = 25pF 15 35 ns ● 45 ns CL = 100pF 20 45 ns ● 60 ns t11 Bus Relinquish Time 8 30 ns 0°C ≤ TA ≤ 70°C ● 35 ns – 40°C ≤ TA ≤ 85°C ● 40 ns t12 RD Low Time ● t10 ns t13 CONVST High Time ● 50 ns t14 Aperture Delay of Sample-and-Hold – 1.5 ns The ● indicates specifications which apply over the full operating
Note 5:
VDD = 5V, fSAMPLE = 800kHz, tr = tf = 5ns unless otherwise temperature range; all other limits and typicals TA = 25°C. specified.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 6:
Linearity, offset and full-scale specifications apply for a single- of a device may be impaired. ended +AIN input with –AIN grounded.
Note 2:
All voltage values are with respect to ground with DGND and
Note 7:
Integral nonlinearity is defined as the deviation of a code from a AGND wired together (unless otherwise noted). straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 3:
When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB when greater than 100mA below VSS or above VDD without latch-up. the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 4:
When these pin voltages are taken below VSS they will be clamped
Note 9:
Guaranteed by design, not subject to test. by internal diodes. This product can handle input currents greater than
Note 10:
Recommended operating conditions. 100mA below VSS without latchup. These pins are not clamped to VDD. 4
W U POWER REQUIRE E TS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ISS Negative Supply Current CS High ● 10 15 mA Nap Mode CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V 10 µA Sleep Mode CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V 1 µA PDISS Power Dissipation ● 80 120 mW Nap Mode CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V 3.8 6 mW Sleep Mode CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V 0.01 mW
W U TI I G CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency ● 800 kHz tCONV Conversion Time ● 900 1250 ns tACQ Acquisition Time ● 150 ns t1 CS to RD Setup Time (Notes 9, 10) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 10 ns t3 NAP/SLP↓ to SHDN↓ Setup Time (Notes 9, 10) ● 10 ns t4 SHDN↑ to CONVST↓ Wake-Up Time (Note 10) 200 ns t5 CONVST Low Time (Notes 10, 11) ● 50 ns t6 CONVST to BUSY Delay CL = 25pF 10 ns ● 60 ns t7 Data Ready Before BUSY↑ 20 35 ns ● 15 ns t8 Delay Between Conversions (Note 10) ● 40 ns t9 Wait Time RD↓ After BUSY↑ ● – 5 ns t10 Data Access Time After RD↓ CL = 25pF 15 35 ns ● 45 ns CL = 100pF 20 45 ns ● 60 ns t11 Bus Relinquish Time 8 30 ns 0°C ≤ TA ≤ 70°C ● 35 ns – 40°C ≤ TA ≤ 85°C ● 40 ns t12 RD Low Time ● t10 ns t13 CONVST High Time ● 50 ns t14 Aperture Delay of Sample-and-Hold – 1.5 ns The ● indicates specifications which apply over the full operating
Note 5:
VDD = 5V, fSAMPLE = 800kHz, tr = tf = 5ns unless otherwise temperature range; all other limits and typicals TA = 25°C. specified.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 6:
Linearity, offset and full-scale specifications apply for a single- of a device may be impaired. ended +AIN input with –AIN grounded.
Note 2:
All voltage values are with respect to ground with DGND and
Note 7:
Integral nonlinearity is defined as the deviation of a code from a AGND wired together (unless otherwise noted). straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 3:
When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB when greater than 100mA below VSS or above VDD without latch-up. the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 4:
When these pin voltages are taken below VSS they will be clamped
Note 9:
Guaranteed by design, not subject to test. by internal diodes. This product can handle input currents greater than
Note 10:
Recommended operating conditions. 100mA below VSS without latchup. These pins are not clamped to VDD. 4
